CTM_BEGIN 2.0 src-cur 11839 20150220200923Z . CTMFS .ctm_status 1004 1004 644 68786773a60d2cfb28c40f4b22e34721 01b90c39ebd7741d6f230b546f8328b6 14 src-cur 11839 CTMFS .svn_revision 1004 1004 644 20a6b6a4bf2a6c348b35c087361a88b1 8faf4c2d3e27efb2a622cdccc54878fe 7 279082 CTMFN release/doc/en_US.ISO8859-1/relnotes/article.xml 1004 1004 644 bedbaa495ed1c67850e9a2f2c84c0d84 0b4599d24e600eab806927878c0178ac 2824 d23 1 a23 1 $FreeBSD: head/release/doc/en_US.ISO8859-1/relnotes/article.xml 279072 2015-02-20 18:42:00Z gjb $ d25 1 a25 1 a304 7 A new device control utility, &man.devctl.8; has been added, which allows making administrative changes to individual devices, such as attaching and detaching drivers, and enabling and disabling devices. The &man.devctl.8; utility uses the new &man.devctl.3; library. a377 6 The &man.xz.1; utility has been udpated to version 5.2.0. The &man.xz.1; utility has been updated to support multi-threaded compression. a462 10 The futimens() and utimensat() system calls have been added. See &man.utimensat.2; for more information. The &man.elf.3; compile-time dependency has been removed from dtri.o, which allows adding DTrace probes to userland applications and libraries without also linking against &man.elf.3;. a517 17 The &man.config.8; utility has been updated to allow using a non-standard src/ tree, specified as an argument to the -s flag. The &os;/&arch.powerpc64; kernel now builds as a position-independent executable, allowing the kernel to be loaded into and run from any physical or virtual address. This change requires an update to &man.loader.8;. The userland and kernel must be updated before rebooting the system. d523 1 a523 4 The &man.hwpmc.4; default and maximum callchain depths have been increased. The default has been increased from 16 to 32, and the maximum increased from 32 to 128. a763 12 General Storage The &man.ctl.4; LUN mapping has been rewritten, replacing iSCSI-specific mapping mechanisms with a new mechanism that works for any port. The &man.ctld.8; utility has been updated to allow controlling non-iSCSI &man.ctl.4; ports. a964 5 The Release Engineering build tools have been updated to use multi-threaded &man.xz.1;. By default, the number of &man.xz.1; threads is set to the number of cores available. CTMFN release/release.conf.sample 1004 1004 644 132febe0aedd0f96704d199ca5505064 742285b7c8333f0bd50a1bb479c6aeff 169 d3 1 a3 1 # $FreeBSD: head/release/release.conf.sample 279074 2015-02-20 18:51:52Z gjb $ a55 3 ## Set to '1' to disable multi-threaded xz(1) compression. #XZ_THREADS=0 CTMFN release/release.sh 1004 1004 755 6099f234ee18d53a3b19f1adc2633482 8f71bf12b604eebd06de2295259b25aa 175 d36 1 a36 1 # $FreeBSD: head/release/release.sh 279074 2015-02-20 18:51:52Z gjb $ a95 1 XZ_THREADS=0 d182 1 a182 1 WITH_CLOUDWARE=${WITH_CLOUDWARE} XZ_THREADS=${XZ_THREADS}" CTMFN share/man/man4/man4.arm/devcfg.4 1004 1004 644 aa31310fb9397716afc39105acee717c 34e6dde48296687a6b8a1abb92e3d786 132 d25 1 a25 1 .\" $FreeBSD: head/share/man/man4/man4.arm/devcfg.4 279051 2015-02-20 11:23:41Z brueffer $ d95 1 a95 1 .An Thomas Skibo CTMFN share/man/man4/man4.i386/apm.4 1004 1004 644 ea3b49ee0ed688b35b94c0636a4d9a81 175b6c38817d9979b0afa16821457ed1 166 d12 1 a12 1 .\" $FreeBSD: head/share/man/man4/man4.i386/apm.4 279054 2015-02-20 13:50:50Z brueffer $ d124 1 a124 1 .An Tatsumi Hosokawa Aq Mt hosokawa@jp.FreeBSD.org CTMFN share/man/man4/man4.powerpc/Makefile 1004 1004 644 281b82f9416c675820e4cc1e36bae865 abeac873374dd4aa10f7f6037785b9be 120 d1 1 a1 1 # $FreeBSD: head/share/man/man4/man4.powerpc/Makefile 279043 2015-02-20 05:40:39Z nwhitehorn $ a8 1 llan.4 \ CTMFM share/man/man4/man4.powerpc/llan.4 1004 1004 644 5063e1b63fc8f6af3f10e3e2172c7d22 2221 .\"- .\" Copyright (c) 2015 Nathan Whitehorn .\" All rights reserved. .\" .\" Redistribution and use in source and binary forms, with or without .\" modification, are permitted provided that the following conditions .\" are met: .\" 1. Redistributions of source code must retain the above copyright .\" notice, this list of conditions and the following disclaimer. .\" 2. Redistributions in binary form must reproduce the above copyright .\" notice, this list of conditions and the following disclaimer in the .\" documentation and/or other materials provided with the distribution. .\" .\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR .\" IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED .\" WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE .\" DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, .\" INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES .\" (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR .\" SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) .\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, .\" STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN .\" ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE .\" POSSIBILITY OF SUCH DAMAGE. .\" .\" $FreeBSD: head/share/man/man4/man4.powerpc/llan.4 279043 2015-02-20 05:40:39Z nwhitehorn $ .\" .Dd February 19, 2015 .Dt LLAN 4 .Os .Sh NAME .Nm llan .Nd POWER Logical Lan .Sh SYNOPSIS To compile this driver into the kernel, place the following lines in your kernel configuration file: .Bd -ragged -offset indent .Cd "device llan" .Ed .Sh DESCRIPTION The .Nm driver provides support for the inter-partition logical LAN controller provided by PAPR-compliant POWER hypervisors (such as PowerVM and PowerKVM). On some firmwares, advanced offload features are supported by the hypervisor, but these are not currently supported by the driver. .Sh SEE ALSO .Xr vtnet 4 , .Xr ifconfig 8 .Sh HISTORY The .Nm device driver appeared in .Fx 10.0. .Sh AUTHORS .An -nosplit The .Nm driver was written by .An Nathan Whitehorn Aq Mt nwhitehorn@FreeBSD.org . CTMFN share/man/man4/man4.powerpc/tsec.4 1004 1004 644 50a7ced0c67755f48348fbfd2f63b000 30f79e9b04962b61234d6e143e3d15e5 630 d26 1 a26 1 .\" $FreeBSD: head/share/man/man4/man4.powerpc/tsec.4 279050 2015-02-20 10:25:13Z brueffer $ d28 1 a28 1 .Dd February 20, 2015 d94 1 a94 2 (whichever occurs first). The following sysctls regulate this behaviour: d101 1 a101 2 Value of 0 for either time or count disables IC on the given path. Time value d103 3 a105 6 to 64 ticks of the TSEC clock. Count 1-255 represents the number of frames (note that value of 1 is equivalent to IC disabled). User provided values larger than supported will be trimmed to the maximum supported. More details d147 1 a147 1 .An Piotr Kruszynski . d149 1 a149 1 .An Rafal Jaworowski . CTMFN share/man/man7/release.7 1004 1004 644 5844f67937bfa549d5f1345414cb143a 41eeaa897c5bc6df512ef3e822702b7e 324 d25 1 a25 1 .\" $FreeBSD: head/share/man/man7/release.7 279073 2015-02-20 18:49:49Z gjb $ d27 1 a27 1 .Dd February 20, 2015 a258 9 .It Va XZ_THREADS Pq Vt int Set to the number of threads .Xr xz 1 should use when compressing images. By default, .Va XZ_THREADS is set to .Va 0 , which uses all available cores on the system. CTMFN sys/dev/sfxge/common/efx.h 1004 1004 644 5903b1ef204ff3bd2355f32be9cbf790 2e5b4a8af6117b4c9f43c85fce801c6c 1316 d25 1 a25 1 * $FreeBSD: head/sys/dev/sfxge/common/efx.h 279077 2015-02-20 19:39:40Z arybchik $ d462 1 a462 1 /* START MKCONFIG GENERATED MonitorHeaderStatsBlock 58706a378332aeee */ a479 14 EFX_MON_STAT_1_2VA, EFX_MON_STAT_VREF, EFX_MON_STAT_VAOE, EFX_MON_STAT_AOE_TEMP, EFX_MON_STAT_PSU_AOE_TEMP, EFX_MON_STAT_PSU_TEMP, EFX_MON_STAT_FAN0, EFX_MON_STAT_FAN1, EFX_MON_STAT_FAN2, EFX_MON_STAT_FAN3, EFX_MON_STAT_FAN4, EFX_MON_STAT_VAOE_IN, EFX_MON_STAT_IAOE, EFX_MON_STAT_IAOE_IN, a863 1 #define EFX_FEATURE_TURBO 0x00000100 a883 1 uint32_t enc_clk_mult; d1601 2 a1602 2 #define EFX_RXQ_MAXNDESCS 4096 #define EFX_RXQ_MINNDESCS 512 d1604 1 a1604 1 #define EFX_RXQ_NDESCS_MASK EFX_MASK(EFX_RXQ_MAXNDESCS, EFX_RXQ_MINNDESCS) d1606 3 a1608 3 #define EFX_RXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t)) #define EFX_RXQ_NBUFS(_ndescs) (EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE) #define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16) d1687 2 a1688 2 #define EFX_TXQ_MAXNDESCS 4096 #define EFX_TXQ_MINNDESCS 512 d1690 1 a1690 1 #define EFX_TXQ_NDESCS_MASK EFX_MASK(EFX_TXQ_MAXNDESCS, EFX_TXQ_MINNDESCS) d1692 3 a1694 3 #define EFX_TXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t)) #define EFX_TXQ_NBUFS(_ndescs) (EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE) #define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16) CTMFN sys/dev/sfxge/common/efx_ev.c 1004 1004 644 1bcaa7633af76325490df8bbf8ef2267 f17786148cf563554cf579f158f272ae 612 d27 1 a27 1 __FBSDID("$FreeBSD: head/sys/dev/sfxge/common/efx_ev.c 279078 2015-02-20 19:42:05Z arybchik $"); a569 6 EFSYS_ASSERT(eecp->eec_link_change != NULL); EFSYS_ASSERT(eecp->eec_exception != NULL); #if EFSYS_OPT_MON_STATS EFSYS_ASSERT(eecp->eec_monitor != NULL); #endif a846 1 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); d853 1 a853 1 if (us > encp->enc_evq_moderation_max) { d872 5 a876 1 timer_val = us * encp->enc_clk_mult / EFX_EV_TIMER_QUANTUM; a878 3 if (timer_val > 0) timer_val--; d882 1 a882 1 FRF_AB_TIMER_VAL, timer_val); d886 1 a886 1 FRF_CZ_TC_TIMER_VAL, timer_val); CTMFN sys/dev/sfxge/common/efx_mcdi.h 1004 1004 644 15de3811b93b488aa5fa5db8f984a613 e47f8648c52612c66919d22f85000c93 200 d25 1 a25 1 * $FreeBSD: head/sys/dev/sfxge/common/efx_mcdi.h 279048 2015-02-20 07:57:59Z arybchik $ a235 3 #define MCDI_CMD_DWORD_FIELD(_edp, _field) \ EFX_DWORD_FIELD(*_edp, MC_CMD_ ## _field) CTMFN sys/dev/sfxge/common/efx_mon.c 1004 1004 644 2fbabc5183428ddb2e66eeb07307eed9 a313dfbb70d7882e7008891cdcc65758 372 d27 1 a27 1 __FBSDID("$FreeBSD: head/sys/dev/sfxge/common/efx_mon.c 279076 2015-02-20 19:37:10Z arybchik $"); d198 1 a198 1 /* START MKCONFIG GENERATED MonitorStatNamesBlock 89ff37f1d74ad8b3 */ a215 14 "1_2va", "vref", "vaoe", "aoe_temperature", "psu_aoe_temperature", "psu_temperature", "fan0", "fan1", "fan2", "fan3", "fan4", "vaoe_in", "iaoe", "iaoe_in", CTMFN sys/dev/sfxge/common/efx_regs_mcdi.h 1004 1004 644 fc8bceb59351df0ebfc0fc84a8fb4655 ba2bda26cc4ba1d2d8130aed6f5a7b46 102154 d25 1 a25 1 * $FreeBSD: head/sys/dev/sfxge/common/efx_regs_mcdi.h 279047 2015-02-20 07:54:35Z arybchik $ a42 12 /* Siena MC shared memmory offsets */ /* The 'doorbell' addresses are hard-wired to alert the MC when written */ #define MC_SMEM_P0_DOORBELL_OFST 0x000 #define MC_SMEM_P1_DOORBELL_OFST 0x004 /* The rest of these are firmware-defined */ #define MC_SMEM_P0_PDU_OFST 0x008 #define MC_SMEM_P1_PDU_OFST 0x108 #define MC_SMEM_PDU_LEN 0x100 #define MC_SMEM_P0_PTP_TIME_OFST 0x7f0 #define MC_SMEM_P0_STATUS_OFST 0x7f8 #define MC_SMEM_P1_STATUS_OFST 0x7fc d61 4 a64 1 /* MCDI version 1 d116 3 a118 1 #ifdef WITH_MCDI_V2 a119 2 #else #define MCDI_CTL_SDU_LEN_MAX 0xfc d136 1 a136 1 * - LEVEL==INFO Command succeeded a295 21 #define MCDI_EVENT_PTP_ERR_TYPE_LBN 0 #define MCDI_EVENT_PTP_ERR_TYPE_WIDTH 8 #define MCDI_EVENT_PTP_ERR_PLL_LOST 0x1 /* enum */ #define MCDI_EVENT_PTP_ERR_FILTER 0x2 /* enum */ #define MCDI_EVENT_PTP_ERR_FIFO 0x3 /* enum */ #define MCDI_EVENT_PTP_ERR_QUEUE 0x4 /* enum */ #define MCDI_EVENT_AOE_ERR_TYPE_LBN 0 #define MCDI_EVENT_AOE_ERR_TYPE_WIDTH 8 #define MCDI_EVENT_AOE_NO_LOAD 0x1 /* enum */ #define MCDI_EVENT_AOE_FC_ASSERT 0x2 /* enum */ #define MCDI_EVENT_AOE_FC_WATCHDOG 0x3 /* enum */ #define MCDI_EVENT_AOE_FC_NO_START 0x4 /* enum */ #define MCDI_EVENT_AOE_FAULT 0x5 /* enum */ #define MCDI_EVENT_AOE_CPLD_REPROGRAMMED 0x6 /* enum */ #define MCDI_EVENT_AOE_LOAD 0x7 /* enum */ #define MCDI_EVENT_AOE_DMA 0x8 /* enum */ #define MCDI_EVENT_AOE_BYTEBLASTER 0x9 /* enum */ #define MCDI_EVENT_AOE_DDR_ECC_STATUS 0xa /* enum */ #define MCDI_EVENT_AOE_PTP_STATUS 0xb /* enum */ #define MCDI_EVENT_AOE_ERR_DATA_LBN 8 #define MCDI_EVENT_AOE_ERR_DATA_WIDTH 8 a315 6 #define MCDI_EVENT_CODE_PTP_RX 0xd /* enum */ #define MCDI_EVENT_CODE_PTP_FAULT 0xe /* enum */ #define MCDI_EVENT_CODE_PTP_PPS 0xf /* enum */ #define MCDI_EVENT_CODE_AOE 0x12 /* enum */ #define MCDI_EVENT_CODE_VCAL_FAIL 0x13 /* enum */ #define MCDI_EVENT_CODE_HW_PPS 0x14 /* enum */ a330 88 #define MCDI_EVENT_PTP_SECONDS_OFST 0 #define MCDI_EVENT_PTP_SECONDS_LBN 0 #define MCDI_EVENT_PTP_SECONDS_WIDTH 32 #define MCDI_EVENT_PTP_NANOSECONDS_OFST 0 #define MCDI_EVENT_PTP_NANOSECONDS_LBN 0 #define MCDI_EVENT_PTP_NANOSECONDS_WIDTH 32 #define MCDI_EVENT_PTP_UUID_OFST 0 #define MCDI_EVENT_PTP_UUID_LBN 0 #define MCDI_EVENT_PTP_UUID_WIDTH 32 /* FCDI_EVENT structuredef */ #define FCDI_EVENT_LEN 8 #define FCDI_EVENT_CONT_LBN 32 #define FCDI_EVENT_CONT_WIDTH 1 #define FCDI_EVENT_LEVEL_LBN 33 #define FCDI_EVENT_LEVEL_WIDTH 3 #define FCDI_EVENT_LEVEL_INFO 0x0 /* enum */ #define FCDI_EVENT_LEVEL_WARN 0x1 /* enum */ #define FCDI_EVENT_LEVEL_ERR 0x2 /* enum */ #define FCDI_EVENT_LEVEL_FATAL 0x3 /* enum */ #define FCDI_EVENT_DATA_OFST 0 #define FCDI_EVENT_LINK_STATE_STATUS_LBN 0 #define FCDI_EVENT_LINK_STATE_STATUS_WIDTH 1 #define FCDI_EVENT_LINK_DOWN 0x0 /* enum */ #define FCDI_EVENT_LINK_UP 0x1 /* enum */ #define FCDI_EVENT_DATA_LBN 0 #define FCDI_EVENT_DATA_WIDTH 32 #define FCDI_EVENT_SRC_LBN 36 #define FCDI_EVENT_SRC_WIDTH 8 #define FCDI_EVENT_EV_CODE_LBN 60 #define FCDI_EVENT_EV_CODE_WIDTH 4 #define FCDI_EVENT_CODE_LBN 44 #define FCDI_EVENT_CODE_WIDTH 8 #define FCDI_EVENT_CODE_REBOOT 0x1 /* enum */ #define FCDI_EVENT_CODE_ASSERT 0x2 /* enum */ #define FCDI_EVENT_CODE_DDR_TEST_RESULT 0x3 /* enum */ #define FCDI_EVENT_CODE_LINK_STATE 0x4 /* enum */ #define FCDI_EVENT_CODE_TIMED_READ 0x5 /* enum */ #define FCDI_EVENT_CODE_PPS_IN 0x6 /* enum */ #define FCDI_EVENT_CODE_PTP_TICK 0x7 /* enum */ #define FCDI_EVENT_CODE_DDR_ECC_STATUS 0x8 /* enum */ #define FCDI_EVENT_CODE_PTP_STATUS 0x9 /* enum */ #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_OFST 0 #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_LBN 0 #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_WIDTH 32 #define FCDI_EVENT_ASSERT_TYPE_LBN 36 #define FCDI_EVENT_ASSERT_TYPE_WIDTH 8 #define FCDI_EVENT_DDR_TEST_RESULT_STATUS_CODE_LBN 36 #define FCDI_EVENT_DDR_TEST_RESULT_STATUS_CODE_WIDTH 8 #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_OFST 0 #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_LBN 0 #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_WIDTH 32 #define FCDI_EVENT_LINK_STATE_DATA_OFST 0 #define FCDI_EVENT_LINK_STATE_DATA_LBN 0 #define FCDI_EVENT_LINK_STATE_DATA_WIDTH 32 #define FCDI_EVENT_PTP_STATE_OFST 0 #define FCDI_EVENT_PTP_UNDEFINED 0x0 /* enum */ #define FCDI_EVENT_PTP_SETUP_FAILED 0x1 /* enum */ #define FCDI_EVENT_PTP_OPERATIONAL 0x2 /* enum */ #define FCDI_EVENT_PTP_STATE_LBN 0 #define FCDI_EVENT_PTP_STATE_WIDTH 32 #define FCDI_EVENT_DDR_ECC_STATUS_BANK_ID_LBN 36 #define FCDI_EVENT_DDR_ECC_STATUS_BANK_ID_WIDTH 8 #define FCDI_EVENT_DDR_ECC_STATUS_STATUS_OFST 0 #define FCDI_EVENT_DDR_ECC_STATUS_STATUS_LBN 0 #define FCDI_EVENT_DDR_ECC_STATUS_STATUS_WIDTH 32 /* FCDI_EXTENDED_EVENT_PPS structuredef */ #define FCDI_EXTENDED_EVENT_PPS_LENMIN 16 #define FCDI_EXTENDED_EVENT_PPS_LENMAX 248 #define FCDI_EXTENDED_EVENT_PPS_LEN(num) (8+8*(num)) #define FCDI_EXTENDED_EVENT_PPS_COUNT_OFST 0 #define FCDI_EXTENDED_EVENT_PPS_COUNT_LBN 0 #define FCDI_EXTENDED_EVENT_PPS_COUNT_WIDTH 32 #define FCDI_EXTENDED_EVENT_PPS_SECONDS_OFST 8 #define FCDI_EXTENDED_EVENT_PPS_SECONDS_LBN 64 #define FCDI_EXTENDED_EVENT_PPS_SECONDS_WIDTH 32 #define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_OFST 12 #define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_LBN 96 #define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_WIDTH 32 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_OFST 8 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LEN 8 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LO_OFST 8 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_HI_OFST 12 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MINNUM 1 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MAXNUM 30 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LBN 64 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_WIDTH 64 a480 2 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_SIENA_BOOTROM 0xb0070000 /* enum */ #define MC_CMD_GET_VERSION_OUT_FIRMWARE_HUNT_BOOTROM 0xb0070001 /* enum */ a496 2053 /* MC_CMD_FC * Perform an FC operation */ #define MC_CMD_FC 0x9 /* MC_CMD_FC_IN msgrequest */ #define MC_CMD_FC_IN_LEN 4 #define MC_CMD_FC_IN_OP_HDR_OFST 0 #define MC_CMD_FC_IN_OP_LBN 0 #define MC_CMD_FC_IN_OP_WIDTH 8 #define MC_CMD_FC_OP_NULL 0x1 /* enum */ #define MC_CMD_FC_OP_UNUSED 0x2 /* enum */ #define MC_CMD_FC_OP_MAC 0x3 /* enum */ #define MC_CMD_FC_OP_READ32 0x4 /* enum */ #define MC_CMD_FC_OP_WRITE32 0x5 /* enum */ #define MC_CMD_FC_OP_TRC_READ 0x6 /* enum */ #define MC_CMD_FC_OP_TRC_WRITE 0x7 /* enum */ #define MC_CMD_FC_OP_GET_VERSION 0x8 /* enum */ #define MC_CMD_FC_OP_TRC_RX_READ 0x9 /* enum */ #define MC_CMD_FC_OP_TRC_RX_WRITE 0xa /* enum */ #define MC_CMD_FC_OP_SFP 0xb /* enum */ #define MC_CMD_FC_OP_DDR_TEST 0xc /* enum */ #define MC_CMD_FC_OP_GET_ASSERT 0xd /* enum */ #define MC_CMD_FC_OP_FPGA_BUILD 0xe /* enum */ #define MC_CMD_FC_OP_READ_MAP 0xf /* enum */ #define MC_CMD_FC_OP_CAPABILITIES 0x10 /* enum */ #define MC_CMD_FC_OP_GLOBAL_FLAGS 0x11 /* enum */ #define MC_CMD_FC_OP_IO_REL 0x12 /* enum */ #define MC_CMD_FC_OP_UHLINK 0x13 /* enum */ #define MC_CMD_FC_OP_SET_LINK 0x14 /* enum */ #define MC_CMD_FC_OP_LICENSE 0x15 /* enum */ #define MC_CMD_FC_OP_STARTUP 0x16 /* enum */ #define MC_CMD_FC_OP_DMA 0x17 /* enum */ #define MC_CMD_FC_OP_TIMED_READ 0x18 /* enum */ #define MC_CMD_FC_OP_LOG 0x19 /* enum */ #define MC_CMD_FC_OP_CLOCK 0x1a /* enum */ #define MC_CMD_FC_OP_DDR 0x1b /* enum */ #define MC_CMD_FC_OP_TIMESTAMP 0x1c /* enum */ #define MC_CMD_FC_OP_SPI 0x1d /* enum */ #define MC_CMD_FC_OP_DIAG 0x1e /* enum */ #define MC_CMD_FC_IN_PORT_EXT_OFST 0x0 /* enum */ #define MC_CMD_FC_IN_PORT_INT_OFST 0x40 /* enum */ /* MC_CMD_FC_IN_NULL msgrequest */ #define MC_CMD_FC_IN_NULL_LEN 4 #define MC_CMD_FC_IN_CMD_OFST 0 /* MC_CMD_FC_IN_MAC msgrequest */ #define MC_CMD_FC_IN_MAC_LEN 8 /* MC_CMD_FC_IN_CMD_OFST 0 */ #define MC_CMD_FC_IN_MAC_HEADER_OFST 4 #define MC_CMD_FC_IN_MAC_OP_LBN 0 #define MC_CMD_FC_IN_MAC_OP_WIDTH 8 #define MC_CMD_FC_OP_MAC_OP_RECONFIGURE 0x1 /* enum */ #define MC_CMD_FC_OP_MAC_OP_SET_LINK 0x2 /* enum */ #define MC_CMD_FC_OP_MAC_OP_GET_STATS 0x3 /* enum */ #define MC_CMD_FC_OP_MAC_OP_GET_RX_STATS 0x6 /* enum */ #define MC_CMD_FC_OP_MAC_OP_GET_TX_STATS 0x7 /* enum */ #define MC_CMD_FC_OP_MAC_OP_READ_STATUS 0x8 /* enum */ #define MC_CMD_FC_IN_MAC_PORT_TYPE_LBN 8 #define MC_CMD_FC_IN_MAC_PORT_TYPE_WIDTH 8 #define MC_CMD_FC_PORT_EXT 0x0 /* enum */ #define MC_CMD_FC_PORT_INT 0x1 /* enum */ #define MC_CMD_FC_IN_MAC_PORT_IDX_LBN 16 #define MC_CMD_FC_IN_MAC_PORT_IDX_WIDTH 8 #define MC_CMD_FC_IN_MAC_CMD_FORMAT_LBN 24 #define MC_CMD_FC_IN_MAC_CMD_FORMAT_WIDTH 8 #define MC_CMD_FC_OP_MAC_CMD_FORMAT_DEFAULT 0x0 /* enum */ #define MC_CMD_FC_OP_MAC_CMD_FORMAT_PORT_OVERRIDE 0x1 /* enum */ /* MC_CMD_FC_IN_MAC_RECONFIGURE msgrequest */ #define MC_CMD_FC_IN_MAC_RECONFIGURE_LEN 8 /* MC_CMD_FC_IN_CMD_OFST 0 */ /* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */ /* MC_CMD_FC_IN_MAC_SET_LINK msgrequest */ #define MC_CMD_FC_IN_MAC_SET_LINK_LEN 32 /* MC_CMD_FC_IN_CMD_OFST 0 */ /* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */ #define MC_CMD_FC_IN_MAC_SET_LINK_MTU_OFST 8 #define MC_CMD_FC_IN_MAC_SET_LINK_DRAIN_OFST 12 #define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_OFST 16 #define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_LEN 8 #define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_LO_OFST 16 #define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_HI_OFST 20 #define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_OFST 24 #define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_UNICAST_LBN 0 #define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_UNICAST_WIDTH 1 #define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_BRDCAST_LBN 1 #define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_BRDCAST_WIDTH 1 #define MC_CMD_FC_IN_MAC_SET_LINK_FCNTL_OFST 28 /* MC_CMD_FC_IN_MAC_READ_STATUS msgrequest */ #define MC_CMD_FC_IN_MAC_READ_STATUS_LEN 8 /* MC_CMD_FC_IN_CMD_OFST 0 */ /* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */ /* MC_CMD_FC_IN_MAC_GET_RX_STATS msgrequest */ #define MC_CMD_FC_IN_MAC_GET_RX_STATS_LEN 8 /* MC_CMD_FC_IN_CMD_OFST 0 */ /* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */ /* MC_CMD_FC_IN_MAC_GET_TX_STATS msgrequest */ #define MC_CMD_FC_IN_MAC_GET_TX_STATS_LEN 8 /* MC_CMD_FC_IN_CMD_OFST 0 */ /* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */ /* MC_CMD_FC_IN_MAC_GET_STATS msgrequest */ #define MC_CMD_FC_IN_MAC_GET_STATS_LEN 20 /* MC_CMD_FC_IN_CMD_OFST 0 */ /* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */ #define MC_CMD_FC_IN_MAC_GET_STATS_STATS_INDEX_OFST 8 #define MC_CMD_FC_IN_MAC_GET_STATS_FLAGS_OFST 12 #define MC_CMD_FC_IN_MAC_GET_STATS_CLEAR_ALL_LBN 0 #define MC_CMD_FC_IN_MAC_GET_STATS_CLEAR_ALL_WIDTH 1 #define MC_CMD_FC_IN_MAC_GET_STATS_CLEAR_LBN 1 #define MC_CMD_FC_IN_MAC_GET_STATS_CLEAR_WIDTH 1 #define MC_CMD_FC_IN_MAC_GET_STATS_UPDATE_LBN 2 #define MC_CMD_FC_IN_MAC_GET_STATS_UPDATE_WIDTH 1 #define MC_CMD_FC_IN_MAC_GET_STATS_NUM_OFST 16 #define MC_CMD_FC_MAC_NSTATS_PER_BLOCK 0x1e /* enum */ #define MC_CMD_FC_MAC_NBYTES_PER_STAT 0x8 /* enum */ /* MC_CMD_FC_IN_READ32 msgrequest */ #define MC_CMD_FC_IN_READ32_LEN 16 /* MC_CMD_FC_IN_CMD_OFST 0 */ #define MC_CMD_FC_IN_READ32_ADDR_HI_OFST 4 #define MC_CMD_FC_IN_READ32_ADDR_LO_OFST 8 #define MC_CMD_FC_IN_READ32_NUMWORDS_OFST 12 /* MC_CMD_FC_IN_WRITE32 msgrequest */ #define MC_CMD_FC_IN_WRITE32_LENMIN 16 #define MC_CMD_FC_IN_WRITE32_LENMAX 252 #define MC_CMD_FC_IN_WRITE32_LEN(num) (12+4*(num)) /* MC_CMD_FC_IN_CMD_OFST 0 */ #define MC_CMD_FC_IN_WRITE32_ADDR_HI_OFST 4 #define MC_CMD_FC_IN_WRITE32_ADDR_LO_OFST 8 #define MC_CMD_FC_IN_WRITE32_BUFFER_OFST 12 #define MC_CMD_FC_IN_WRITE32_BUFFER_LEN 4 #define MC_CMD_FC_IN_WRITE32_BUFFER_MINNUM 1 #define MC_CMD_FC_IN_WRITE32_BUFFER_MAXNUM 60 /* MC_CMD_FC_IN_TRC_READ msgrequest */ #define MC_CMD_FC_IN_TRC_READ_LEN 12 /* MC_CMD_FC_IN_CMD_OFST 0 */ #define MC_CMD_FC_IN_TRC_READ_TRC_OFST 4 #define MC_CMD_FC_IN_TRC_READ_CHANNEL_OFST 8 /* MC_CMD_FC_IN_TRC_WRITE msgrequest */ #define MC_CMD_FC_IN_TRC_WRITE_LEN 28 /* MC_CMD_FC_IN_CMD_OFST 0 */ #define MC_CMD_FC_IN_TRC_WRITE_TRC_OFST 4 #define MC_CMD_FC_IN_TRC_WRITE_CHANNEL_OFST 8 #define MC_CMD_FC_IN_TRC_WRITE_DATA_OFST 12 #define MC_CMD_FC_IN_TRC_WRITE_DATA_LEN 4 #define MC_CMD_FC_IN_TRC_WRITE_DATA_NUM 4 /* MC_CMD_FC_IN_GET_VERSION msgrequest */ #define MC_CMD_FC_IN_GET_VERSION_LEN 4 /* MC_CMD_FC_IN_CMD_OFST 0 */ /* MC_CMD_FC_IN_TRC_RX_READ msgrequest */ #define MC_CMD_FC_IN_TRC_RX_READ_LEN 12 /* MC_CMD_FC_IN_CMD_OFST 0 */ #define MC_CMD_FC_IN_TRC_RX_READ_TRC_OFST 4 #define MC_CMD_FC_IN_TRC_RX_READ_CHANNEL_OFST 8 /* MC_CMD_FC_IN_TRC_RX_WRITE msgrequest */ #define MC_CMD_FC_IN_TRC_RX_WRITE_LEN 20 /* MC_CMD_FC_IN_CMD_OFST 0 */ #define MC_CMD_FC_IN_TRC_RX_WRITE_TRC_OFST 4 #define MC_CMD_FC_IN_TRC_RX_WRITE_CHANNEL_OFST 8 #define MC_CMD_FC_IN_TRC_RX_WRITE_DATA_OFST 12 #define MC_CMD_FC_IN_TRC_RX_WRITE_DATA_LEN 4 #define MC_CMD_FC_IN_TRC_RX_WRITE_DATA_NUM 2 /* MC_CMD_FC_IN_SFP msgrequest */ #define MC_CMD_FC_IN_SFP_LEN 24 /* MC_CMD_FC_IN_CMD_OFST 0 */ #define MC_CMD_FC_IN_SFP_SPEED_OFST 4 #define MC_CMD_FC_IN_SFP_COPPER_LEN_OFST 8 #define MC_CMD_FC_IN_SFP_DUAL_SPEED_OFST 12 #define MC_CMD_FC_IN_SFP_PRESENT_OFST 16 #define MC_CMD_FC_IN_SFP_TYPE_OFST 20 /* MC_CMD_FC_IN_DDR_TEST msgrequest */ #define MC_CMD_FC_IN_DDR_TEST_LEN 8 /* MC_CMD_FC_IN_CMD_OFST 0 */ #define MC_CMD_FC_IN_DDR_TEST_HEADER_OFST 4 #define MC_CMD_FC_IN_DDR_TEST_OP_LBN 0 #define MC_CMD_FC_IN_DDR_TEST_OP_WIDTH 8 #define MC_CMD_FC_OP_DDR_TEST_START 0x1 /* enum */ #define MC_CMD_FC_OP_DDR_TEST_POLL 0x2 /* enum */ /* MC_CMD_FC_IN_DDR_TEST_START msgrequest */ #define MC_CMD_FC_IN_DDR_TEST_START_LEN 12 /* MC_CMD_FC_IN_CMD_OFST 0 */ /* MC_CMD_FC_IN_DDR_TEST_HEADER_OFST 4 */ #define MC_CMD_FC_IN_DDR_TEST_START_MASK_OFST 8 #define MC_CMD_FC_IN_DDR_TEST_START_T0_LBN 0 #define MC_CMD_FC_IN_DDR_TEST_START_T0_WIDTH 1 #define MC_CMD_FC_IN_DDR_TEST_START_T1_LBN 1 #define MC_CMD_FC_IN_DDR_TEST_START_T1_WIDTH 1 #define MC_CMD_FC_IN_DDR_TEST_START_B0_LBN 2 #define MC_CMD_FC_IN_DDR_TEST_START_B0_WIDTH 1 #define MC_CMD_FC_IN_DDR_TEST_START_B1_LBN 3 #define MC_CMD_FC_IN_DDR_TEST_START_B1_WIDTH 1 /* MC_CMD_FC_IN_DDR_TEST_POLL msgrequest */ #define MC_CMD_FC_IN_DDR_TEST_POLL_LEN 8 #define MC_CMD_FC_IN_DDR_TEST_CMD_OFST 0 /* MC_CMD_FC_IN_DDR_TEST_HEADER_OFST 4 */ /* MC_CMD_FC_IN_GET_ASSERT msgrequest */ #define MC_CMD_FC_IN_GET_ASSERT_LEN 4 /* MC_CMD_FC_IN_CMD_OFST 0 */ /* MC_CMD_FC_IN_FPGA_BUILD msgrequest */ #define MC_CMD_FC_IN_FPGA_BUILD_LEN 8 /* MC_CMD_FC_IN_CMD_OFST 0 */ #define MC_CMD_FC_IN_FPGA_BUILD_OP_OFST 4 #define MC_CMD_FC_IN_FPGA_BUILD_BUILD 0x1 /* enum */ #define MC_CMD_FC_IN_FPGA_BUILD_SERVICES 0x2 /* enum */ #define MC_CMD_FC_IN_FPGA_BUILD_BSP_VERSION 0x3 /* enum */ /* MC_CMD_FC_IN_READ_MAP msgrequest */ #define MC_CMD_FC_IN_READ_MAP_LEN 8 /* MC_CMD_FC_IN_CMD_OFST 0 */ #define MC_CMD_FC_IN_READ_MAP_HEADER_OFST 4 #define MC_CMD_FC_IN_READ_MAP_OP_LBN 0 #define MC_CMD_FC_IN_READ_MAP_OP_WIDTH 8 #define MC_CMD_FC_OP_READ_MAP_COUNT 0x1 /* enum */ #define MC_CMD_FC_OP_READ_MAP_INDEX 0x2 /* enum */ /* MC_CMD_FC_IN_READ_MAP_COUNT msgrequest */ #define MC_CMD_FC_IN_READ_MAP_COUNT_LEN 8 /* MC_CMD_FC_IN_CMD_OFST 0 */ /* MC_CMD_FC_IN_READ_MAP_HEADER_OFST 4 */ /* MC_CMD_FC_IN_READ_MAP_INDEX msgrequest */ #define MC_CMD_FC_IN_READ_MAP_INDEX_LEN 12 /* MC_CMD_FC_IN_CMD_OFST 0 */ /* MC_CMD_FC_IN_READ_MAP_HEADER_OFST 4 */ #define MC_CMD_FC_IN_MAP_INDEX_OFST 8 /* MC_CMD_FC_IN_CAPABILITIES msgrequest */ #define MC_CMD_FC_IN_CAPABILITIES_LEN 4 /* MC_CMD_FC_IN_CMD_OFST 0 */ /* MC_CMD_FC_IN_GLOBAL_FLAGS msgrequest */ #define MC_CMD_FC_IN_GLOBAL_FLAGS_LEN 8 /* MC_CMD_FC_IN_CMD_OFST 0 */ #define MC_CMD_FC_IN_GLOBAL_FLAGS_FLAGS_OFST 4 #define MC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_CABLE_PLUGGED_IN_LBN 0 #define MC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_CABLE_PLUGGED_IN_WIDTH 1 #define MC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_LINK_MONITORING_LBN 1 #define MC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_LINK_MONITORING_WIDTH 1 #define MC_CMD_FC_IN_GLOBAL_FLAGS_DFE_ENABLE_LBN 2 #define MC_CMD_FC_IN_GLOBAL_FLAGS_DFE_ENABLE_WIDTH 1 #define MC_CMD_FC_IN_GLOBAL_FLAGS_1D_EYE_ENABLE_LBN 3 #define MC_CMD_FC_IN_GLOBAL_FLAGS_1D_EYE_ENABLE_WIDTH 1 #define MC_CMD_FC_IN_GLOBAL_FLAGS_1D_TUNING_ENABLE_LBN 4 #define MC_CMD_FC_IN_GLOBAL_FLAGS_1D_TUNING_ENABLE_WIDTH 1 #define MC_CMD_FC_IN_GLOBAL_FLAGS_OFFCAL_ENABLE_LBN 5 #define MC_CMD_FC_IN_GLOBAL_FLAGS_OFFCAL_ENABLE_WIDTH 1 /* MC_CMD_FC_IN_IO_REL msgrequest */ #define MC_CMD_FC_IN_IO_REL_LEN 8 /* MC_CMD_FC_IN_CMD_OFST 0 */ #define MC_CMD_FC_IN_IO_REL_HEADER_OFST 4 #define MC_CMD_FC_IN_IO_REL_OP_LBN 0 #define MC_CMD_FC_IN_IO_REL_OP_WIDTH 8 #define MC_CMD_FC_IN_IO_REL_GET_ADDR 0x1 /* enum */ #define MC_CMD_FC_IN_IO_REL_READ32 0x2 /* enum */ #define MC_CMD_FC_IN_IO_REL_WRITE32 0x3 /* enum */ #define MC_CMD_FC_IN_IO_REL_COMP_TYPE_LBN 8 #define MC_CMD_FC_IN_IO_REL_COMP_TYPE_WIDTH 8 #define MC_CMD_FC_COMP_TYPE_APP_ADDR_SPACE 0x1 /* enum */ #define MC_CMD_FC_COMP_TYPE_FLASH 0x2 /* enum */ /* MC_CMD_FC_IN_IO_REL_GET_ADDR msgrequest */ #define MC_CMD_FC_IN_IO_REL_GET_ADDR_LEN 8 /* MC_CMD_FC_IN_CMD_OFST 0 */ /* MC_CMD_FC_IN_IO_REL_HEADER_OFST 4 */ /* MC_CMD_FC_IN_IO_REL_READ32 msgrequest */ #define MC_CMD_FC_IN_IO_REL_READ32_LEN 20 /* MC_CMD_FC_IN_CMD_OFST 0 */ /* MC_CMD_FC_IN_IO_REL_HEADER_OFST 4 */ #define MC_CMD_FC_IN_IO_REL_READ32_ADDR_HI_OFST 8 #define MC_CMD_FC_IN_IO_REL_READ32_ADDR_LO_OFST 12 #define MC_CMD_FC_IN_IO_REL_READ32_NUMWORDS_OFST 16 /* MC_CMD_FC_IN_IO_REL_WRITE32 msgrequest */ #define MC_CMD_FC_IN_IO_REL_WRITE32_LENMIN 20 #define MC_CMD_FC_IN_IO_REL_WRITE32_LENMAX 252 #define MC_CMD_FC_IN_IO_REL_WRITE32_LEN(num) (16+4*(num)) /* MC_CMD_FC_IN_CMD_OFST 0 */ /* MC_CMD_FC_IN_IO_REL_HEADER_OFST 4 */ #define MC_CMD_FC_IN_IO_REL_WRITE32_ADDR_HI_OFST 8 #define MC_CMD_FC_IN_IO_REL_WRITE32_ADDR_LO_OFST 12 #define MC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_OFST 16 #define MC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_LEN 4 #define MC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_MINNUM 1 #define MC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_MAXNUM 59 /* MC_CMD_FC_IN_UHLINK msgrequest */ #define MC_CMD_FC_IN_UHLINK_LEN 8 /* MC_CMD_FC_IN_CMD_OFST 0 */ #define MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 #define MC_CMD_FC_IN_UHLINK_OP_LBN 0 #define MC_CMD_FC_IN_UHLINK_OP_WIDTH 8 #define MC_CMD_FC_OP_UHLINK_PHY 0x1 /* enum */ #define MC_CMD_FC_OP_UHLINK_MAC 0x2 /* enum */ #define MC_CMD_FC_OP_UHLINK_RX_EYE 0x3 /* enum */ #define MC_CMD_FC_OP_UHLINK_DUMP_RX_EYE_PLOT 0x4 /* enum */ #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT 0x5 /* enum */ #define MC_CMD_FC_OP_UHLINK_RX_TUNE 0x6 /* enum */ #define MC_CMD_FC_OP_UHLINK_LOOPBACK_SET 0x7 /* enum */ #define MC_CMD_FC_OP_UHLINK_LOOPBACK_GET 0x8 /* enum */ #define MC_CMD_FC_IN_UHLINK_PORT_TYPE_LBN 8 #define MC_CMD_FC_IN_UHLINK_PORT_TYPE_WIDTH 8 #define MC_CMD_FC_IN_UHLINK_PORT_IDX_LBN 16 #define MC_CMD_FC_IN_UHLINK_PORT_IDX_WIDTH 8 #define MC_CMD_FC_IN_UHLINK_CMD_FORMAT_LBN 24 #define MC_CMD_FC_IN_UHLINK_CMD_FORMAT_WIDTH 8 #define MC_CMD_FC_OP_UHLINK_CMD_FORMAT_DEFAULT 0x0 /* enum */ #define MC_CMD_FC_OP_UHLINK_CMD_FORMAT_PORT_OVERRIDE 0x1 /* enum */ /* MC_CMD_FC_OP_UHLINK_PHY msgrequest */ #define MC_CMD_FC_OP_UHLINK_PHY_LEN 8 /* MC_CMD_FC_IN_CMD_OFST 0 */ /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ /* MC_CMD_FC_OP_UHLINK_MAC msgrequest */ #define MC_CMD_FC_OP_UHLINK_MAC_LEN 8 /* MC_CMD_FC_IN_CMD_OFST 0 */ /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ /* MC_CMD_FC_OP_UHLINK_RX_EYE msgrequest */ #define MC_CMD_FC_OP_UHLINK_RX_EYE_LEN 12 /* MC_CMD_FC_IN_CMD_OFST 0 */ /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ #define MC_CMD_FC_OP_UHLINK_RX_EYE_INDEX_OFST 8 #define MC_CMD_FC_UHLINK_RX_EYE_PER_BLOCK 0x30 /* enum */ /* MC_CMD_FC_OP_UHLINK_DUMP_RX_EYE_PLOT msgrequest */ #define MC_CMD_FC_OP_UHLINK_DUMP_RX_EYE_PLOT_LEN 8 /* MC_CMD_FC_IN_CMD_OFST 0 */ /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ /* MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT msgrequest */ #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_LEN 20 /* MC_CMD_FC_IN_CMD_OFST 0 */ /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_DC_GAIN_OFST 8 #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_EQ_CONTROL_OFST 12 #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_INDEX_OFST 16 #define MC_CMD_FC_UHLINK_RX_EYE_PLOT_ROWS_PER_BLOCK 0x1e /* enum */ /* MC_CMD_FC_OP_UHLINK_RX_TUNE msgrequest */ #define MC_CMD_FC_OP_UHLINK_RX_TUNE_LEN 8 /* MC_CMD_FC_IN_CMD_OFST 0 */ /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ /* MC_CMD_FC_OP_UHLINK_LOOPBACK_SET msgrequest */ #define MC_CMD_FC_OP_UHLINK_LOOPBACK_SET_LEN 16 /* MC_CMD_FC_IN_CMD_OFST 0 */ /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ #define MC_CMD_FC_OP_UHLINK_LOOPBACK_SET_TYPE_OFST 8 #define MC_CMD_FC_UHLINK_LOOPBACK_TYPE_PCS_SERIAL 0x0 /* enum */ #define MC_CMD_FC_UHLINK_LOOPBACK_TYPE_PMA_PRE_CDR 0x1 /* enum */ #define MC_CMD_FC_UHLINK_LOOPBACK_TYPE_PMA_POST_CDR 0x2 /* enum */ #define MC_CMD_FC_OP_UHLINK_LOOPBACK_SET_STATE_OFST 12 #define MC_CMD_FC_UHLINK_LOOPBACK_STATE_OFF 0x0 /* enum */ #define MC_CMD_FC_UHLINK_LOOPBACK_STATE_ON 0x1 /* enum */ /* MC_CMD_FC_OP_UHLINK_LOOPBACK_GET msgrequest */ #define MC_CMD_FC_OP_UHLINK_LOOPBACK_GET_LEN 12 /* MC_CMD_FC_IN_CMD_OFST 0 */ /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ #define MC_CMD_FC_OP_UHLINK_LOOPBACK_GET_TYPE_OFST 8 /* MC_CMD_FC_IN_SET_LINK msgrequest */ #define MC_CMD_FC_IN_SET_LINK_LEN 16 /* MC_CMD_FC_IN_CMD_OFST 0 */ #define MC_CMD_FC_IN_SET_LINK_MODE_OFST 4 #define MC_CMD_FC_IN_SET_LINK_SPEED_OFST 8 #define MC_CMD_FC_IN_SET_LINK_FLAGS_OFST 12 #define MC_CMD_FC_IN_SET_LINK_LOWPOWER_LBN 0 #define MC_CMD_FC_IN_SET_LINK_LOWPOWER_WIDTH 1 #define MC_CMD_FC_IN_SET_LINK_POWEROFF_LBN 1 #define MC_CMD_FC_IN_SET_LINK_POWEROFF_WIDTH 1 #define MC_CMD_FC_IN_SET_LINK_TXDIS_LBN 2 #define MC_CMD_FC_IN_SET_LINK_TXDIS_WIDTH 1 /* MC_CMD_FC_IN_LICENSE msgrequest */ #define MC_CMD_FC_IN_LICENSE_LEN 8 /* MC_CMD_FC_IN_CMD_OFST 0 */ #define MC_CMD_FC_IN_LICENSE_OP_OFST 4 #define MC_CMD_FC_IN_LICENSE_UPDATE_LICENSE 0x0 /* enum */ #define MC_CMD_FC_IN_LICENSE_GET_KEY_STATS 0x1 /* enum */ /* MC_CMD_FC_IN_STARTUP msgrequest */ #define MC_CMD_FC_IN_STARTUP_LEN 40 /* MC_CMD_FC_IN_CMD_OFST 0 */ #define MC_CMD_FC_IN_STARTUP_BASE_OFST 4 #define MC_CMD_FC_IN_STARTUP_LENGTH_OFST 8 #define MC_CMD_FC_IN_STARTUP_IDLENGTH_OFST 12 #define MC_CMD_FC_IN_STARTUP_ID_OFST 16 #define MC_CMD_FC_IN_STARTUP_ID_LEN 1 #define MC_CMD_FC_IN_STARTUP_ID_NUM 24 /* MC_CMD_FC_IN_DMA msgrequest */ #define MC_CMD_FC_IN_DMA_LEN 8 /* MC_CMD_FC_IN_CMD_OFST 0 */ #define MC_CMD_FC_IN_DMA_OP_OFST 4 #define MC_CMD_FC_IN_DMA_STOP 0x0 /* enum */ #define MC_CMD_FC_IN_DMA_READ 0x1 /* enum */ /* MC_CMD_FC_IN_DMA_STOP msgrequest */ #define MC_CMD_FC_IN_DMA_STOP_LEN 12 /* MC_CMD_FC_IN_CMD_OFST 0 */ /* MC_CMD_FC_IN_DMA_OP_OFST 4 */ #define MC_CMD_FC_IN_DMA_STOP_FC_HANDLE_OFST 8 /* MC_CMD_FC_IN_DMA_READ msgrequest */ #define MC_CMD_FC_IN_DMA_READ_LEN 16 /* MC_CMD_FC_IN_CMD_OFST 0 */ /* MC_CMD_FC_IN_DMA_OP_OFST 4 */ #define MC_CMD_FC_IN_DMA_READ_OFFSET_OFST 8 #define MC_CMD_FC_IN_DMA_READ_LENGTH_OFST 12 /* MC_CMD_FC_IN_TIMED_READ msgrequest */ #define MC_CMD_FC_IN_TIMED_READ_LEN 8 /* MC_CMD_FC_IN_CMD_OFST 0 */ #define MC_CMD_FC_IN_TIMED_READ_OP_OFST 4 #define MC_CMD_FC_IN_TIMED_READ_SET 0x0 /* enum */ #define MC_CMD_FC_IN_TIMED_READ_GET 0x1 /* enum */ #define MC_CMD_FC_IN_TIMED_READ_CLEAR 0x2 /* enum */ /* MC_CMD_FC_IN_TIMED_READ_SET msgrequest */ #define MC_CMD_FC_IN_TIMED_READ_SET_LEN 52 /* MC_CMD_FC_IN_CMD_OFST 0 */ /* MC_CMD_FC_IN_TIMED_READ_OP_OFST 4 */ #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_HANDLE_OFST 8 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_OFST 12 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_LEN 8 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_LO_OFST 12 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_HI_OFST 16 #define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_OFST 20 #define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_LEN 8 #define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_LO_OFST 20 #define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_HI_OFST 24 #define MC_CMD_FC_IN_TIMED_READ_SET_AOE_LENGTH_OFST 28 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_LENGTH_OFST 32 #define MC_CMD_FC_IN_TIMED_READ_SET_OFFSET_OFST 36 #define MC_CMD_FC_IN_TIMED_READ_SET_DATA_OFST 40 #define MC_CMD_FC_IN_TIMED_READ_SET_FLAGS_OFST 44 #define MC_CMD_FC_IN_TIMED_READ_SET_INDIRECT_LBN 0 #define MC_CMD_FC_IN_TIMED_READ_SET_INDIRECT_WIDTH 1 #define MC_CMD_FC_IN_TIMED_READ_SET_DOUBLE_LBN 1 #define MC_CMD_FC_IN_TIMED_READ_SET_DOUBLE_WIDTH 1 #define MC_CMD_FC_IN_TIMED_READ_SET_EVENT_LBN 2 #define MC_CMD_FC_IN_TIMED_READ_SET_EVENT_WIDTH 1 #define MC_CMD_FC_IN_TIMED_READ_SET_PREREAD_LBN 3 #define MC_CMD_FC_IN_TIMED_READ_SET_PREREAD_WIDTH 2 #define MC_CMD_FC_IN_TIMED_READ_SET_NONE 0x0 /* enum */ #define MC_CMD_FC_IN_TIMED_READ_SET_READ 0x1 /* enum */ #define MC_CMD_FC_IN_TIMED_READ_SET_WRITE 0x2 /* enum */ #define MC_CMD_FC_IN_TIMED_READ_SET_READWRITE 0x3 /* enum */ #define MC_CMD_FC_IN_TIMED_READ_SET_PERIOD_OFST 48 /* MC_CMD_FC_IN_TIMED_READ_GET msgrequest */ #define MC_CMD_FC_IN_TIMED_READ_GET_LEN 12 /* MC_CMD_FC_IN_CMD_OFST 0 */ /* MC_CMD_FC_IN_TIMED_READ_OP_OFST 4 */ #define MC_CMD_FC_IN_TIMED_READ_GET_FC_HANDLE_OFST 8 /* MC_CMD_FC_IN_TIMED_READ_CLEAR msgrequest */ #define MC_CMD_FC_IN_TIMED_READ_CLEAR_LEN 12 /* MC_CMD_FC_IN_CMD_OFST 0 */ /* MC_CMD_FC_IN_TIMED_READ_OP_OFST 4 */ #define MC_CMD_FC_IN_TIMED_READ_CLEAR_FC_HANDLE_OFST 8 /* MC_CMD_FC_IN_LOG msgrequest */ #define MC_CMD_FC_IN_LOG_LEN 8 /* MC_CMD_FC_IN_CMD_OFST 0 */ #define MC_CMD_FC_IN_LOG_OP_OFST 4 #define MC_CMD_FC_IN_LOG_ADDR_RANGE 0x0 /* enum */ #define MC_CMD_FC_IN_LOG_JTAG_UART 0x1 /* enum */ /* MC_CMD_FC_IN_LOG_ADDR_RANGE msgrequest */ #define MC_CMD_FC_IN_LOG_ADDR_RANGE_LEN 20 /* MC_CMD_FC_IN_CMD_OFST 0 */ /* MC_CMD_FC_IN_LOG_OP_OFST 4 */ #define MC_CMD_FC_IN_LOG_ADDR_RANGE_OFFSET_OFST 8 #define MC_CMD_FC_IN_LOG_ADDR_RANGE_LENGTH_OFST 12 #define MC_CMD_FC_IN_LOG_ADDR_RANGE_ERASE_SIZE_OFST 16 /* MC_CMD_FC_IN_LOG_JTAG_UART msgrequest */ #define MC_CMD_FC_IN_LOG_JTAG_UART_LEN 12 /* MC_CMD_FC_IN_CMD_OFST 0 */ /* MC_CMD_FC_IN_LOG_OP_OFST 4 */ #define MC_CMD_FC_IN_LOG_JTAG_UART_ENABLE_OFST 8 /* MC_CMD_FC_IN_CLOCK msgrequest */ #define MC_CMD_FC_IN_CLOCK_LEN 12 /* MC_CMD_FC_IN_CMD_OFST 0 */ #define MC_CMD_FC_IN_CLOCK_OP_OFST 4 #define MC_CMD_FC_IN_CLOCK_GET_TIME 0x0 /* enum */ #define MC_CMD_FC_IN_CLOCK_SET_TIME 0x1 /* enum */ #define MC_CMD_FC_IN_CLOCK_ID_OFST 8 #define MC_CMD_FC_IN_CLOCK_STATS 0x0 /* enum */ #define MC_CMD_FC_IN_CLOCK_MAC 0x1 /* enum */ /* MC_CMD_FC_IN_CLOCK_GET_TIME msgrequest */ #define MC_CMD_FC_IN_CLOCK_GET_TIME_LEN 12 /* MC_CMD_FC_IN_CMD_OFST 0 */ /* MC_CMD_FC_IN_CLOCK_OP_OFST 4 */ /* MC_CMD_FC_IN_CLOCK_ID_OFST 8 */ /* MC_CMD_FC_IN_CLOCK_SET_TIME msgrequest */ #define MC_CMD_FC_IN_CLOCK_SET_TIME_LEN 24 /* MC_CMD_FC_IN_CMD_OFST 0 */ /* MC_CMD_FC_IN_CLOCK_OP_OFST 4 */ /* MC_CMD_FC_IN_CLOCK_ID_OFST 8 */ #define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_OFST 12 #define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_LEN 8 #define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_LO_OFST 12 #define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_HI_OFST 16 #define MC_CMD_FC_IN_CLOCK_SET_TIME_NANOSECONDS_OFST 20 /* MC_CMD_FC_IN_DDR msgrequest */ #define MC_CMD_FC_IN_DDR_LEN 12 /* MC_CMD_FC_IN_CMD_OFST 0 */ #define MC_CMD_FC_IN_DDR_OP_OFST 4 #define MC_CMD_FC_IN_DDR_SET_SPD 0x0 /* enum */ #define MC_CMD_FC_IN_DDR_GET_STATUS 0x1 /* enum */ #define MC_CMD_FC_IN_DDR_BANK_OFST 8 #define MC_CMD_FC_IN_DDR_BANK_B0 0x0 /* enum */ #define MC_CMD_FC_IN_DDR_BANK_B1 0x1 /* enum */ #define MC_CMD_FC_IN_DDR_BANK_T0 0x2 /* enum */ #define MC_CMD_FC_IN_DDR_BANK_T1 0x3 /* enum */ #define MC_CMD_FC_IN_DDR_NUM_BANKS 0x4 /* enum */ /* MC_CMD_FC_IN_DDR_SET_SPD msgrequest */ #define MC_CMD_FC_IN_DDR_SET_SPD_LEN 148 /* MC_CMD_FC_IN_CMD_OFST 0 */ /* MC_CMD_FC_IN_DDR_OP_OFST 4 */ /* MC_CMD_FC_IN_DDR_BANK_OFST 8 */ #define MC_CMD_FC_IN_DDR_FLAGS_OFST 12 #define MC_CMD_FC_IN_DDR_SET_SPD_ACTIVE 0x1 /* enum */ #define MC_CMD_FC_IN_DDR_SPD_OFST 16 #define MC_CMD_FC_IN_DDR_SPD_LEN 1 #define MC_CMD_FC_IN_DDR_SPD_NUM 128 #define MC_CMD_FC_IN_DDR_SPD_PAGE_ID_OFST 144 /* MC_CMD_FC_IN_DDR_GET_STATUS msgrequest */ #define MC_CMD_FC_IN_DDR_GET_STATUS_LEN 12 /* MC_CMD_FC_IN_CMD_OFST 0 */ /* MC_CMD_FC_IN_DDR_OP_OFST 4 */ /* MC_CMD_FC_IN_DDR_BANK_OFST 8 */ /* MC_CMD_FC_IN_TIMESTAMP msgrequest */ #define MC_CMD_FC_IN_TIMESTAMP_LEN 8 /* MC_CMD_FC_IN_CMD_OFST 0 */ #define MC_CMD_FC_IN_TIMESTAMP_OP_OFST 4 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT 0x0 /* enum */ #define MC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT 0x1 /* enum */ #define MC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT 0x2 /* enum */ /* MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT msgrequest */ #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_LEN 28 /* MC_CMD_FC_IN_CMD_OFST 0 */ #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_OP_OFST 4 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_FILTER_OFST 8 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_LATEST 0x0 /* enum */ #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_MATCH 0x1 /* enum */ #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_OFST 12 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_LEN 8 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_LO_OFST 12 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_HI_OFST 16 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_PORT_NUM_OFST 20 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_SEQ_NUM_OFST 24 /* MC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT msgrequest */ #define MC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT_LEN 8 /* MC_CMD_FC_IN_CMD_OFST 0 */ #define MC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT_OP_OFST 4 /* MC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT msgrequest */ #define MC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT_LEN 8 /* MC_CMD_FC_IN_CMD_OFST 0 */ #define MC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT_OP_OFST 4 /* MC_CMD_FC_IN_SPI msgrequest */ #define MC_CMD_FC_IN_SPI_LEN 8 /* MC_CMD_FC_IN_CMD_OFST 0 */ #define MC_CMD_FC_IN_SPI_OP_OFST 4 #define MC_CMD_FC_IN_SPI_READ 0x0 /* enum */ #define MC_CMD_FC_IN_SPI_WRITE 0x1 /* enum */ #define MC_CMD_FC_IN_SPI_ERASE 0x2 /* enum */ /* MC_CMD_FC_IN_SPI_READ msgrequest */ #define MC_CMD_FC_IN_SPI_READ_LEN 16 /* MC_CMD_FC_IN_CMD_OFST 0 */ #define MC_CMD_FC_IN_SPI_READ_OP_OFST 4 #define MC_CMD_FC_IN_SPI_READ_ADDR_OFST 8 #define MC_CMD_FC_IN_SPI_READ_NUMBYTES_OFST 12 /* MC_CMD_FC_IN_SPI_WRITE msgrequest */ #define MC_CMD_FC_IN_SPI_WRITE_LENMIN 16 #define MC_CMD_FC_IN_SPI_WRITE_LENMAX 252 #define MC_CMD_FC_IN_SPI_WRITE_LEN(num) (12+4*(num)) /* MC_CMD_FC_IN_CMD_OFST 0 */ #define MC_CMD_FC_IN_SPI_WRITE_OP_OFST 4 #define MC_CMD_FC_IN_SPI_WRITE_ADDR_OFST 8 #define MC_CMD_FC_IN_SPI_WRITE_BUFFER_OFST 12 #define MC_CMD_FC_IN_SPI_WRITE_BUFFER_LEN 4 #define MC_CMD_FC_IN_SPI_WRITE_BUFFER_MINNUM 1 #define MC_CMD_FC_IN_SPI_WRITE_BUFFER_MAXNUM 60 /* MC_CMD_FC_IN_SPI_ERASE msgrequest */ #define MC_CMD_FC_IN_SPI_ERASE_LEN 16 /* MC_CMD_FC_IN_CMD_OFST 0 */ #define MC_CMD_FC_IN_SPI_ERASE_OP_OFST 4 #define MC_CMD_FC_IN_SPI_ERASE_ADDR_OFST 8 #define MC_CMD_FC_IN_SPI_ERASE_NUMBYTES_OFST 12 /* MC_CMD_FC_IN_DIAG msgrequest */ #define MC_CMD_FC_IN_DIAG_LEN 8 /* MC_CMD_FC_IN_CMD_OFST 0 */ #define MC_CMD_FC_IN_DIAG_OP_OFST 4 #define MC_CMD_FC_IN_DIAG_POWER_NOISE 0x0 /* enum */ #define MC_CMD_FC_IN_DIAG_DDR_SOAK 0x1 /* enum */ #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL 0x2 /* enum */ /* MC_CMD_FC_IN_DIAG_POWER_NOISE msgrequest */ #define MC_CMD_FC_IN_DIAG_POWER_NOISE_LEN 12 /* MC_CMD_FC_IN_CMD_OFST 0 */ #define MC_CMD_FC_IN_DIAG_POWER_NOISE_OP_OFST 4 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_SUB_OP_OFST 8 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG 0x0 /* enum */ #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG 0x1 /* enum */ /* MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG msgrequest */ #define MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG_LEN 12 /* MC_CMD_FC_IN_CMD_OFST 0 */ #define MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG_OP_OFST 4 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG_SUB_OP_OFST 8 /* MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG msgrequest */ #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_LEN 20 /* MC_CMD_FC_IN_CMD_OFST 0 */ #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_OP_OFST 4 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_SUB_OP_OFST 8 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_TOGGLE_COUNT_OFST 12 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_CLKEN_COUNT_OFST 16 /* MC_CMD_FC_IN_DIAG_DDR_SOAK msgrequest */ #define MC_CMD_FC_IN_DIAG_DDR_SOAK_LEN 12 /* MC_CMD_FC_IN_CMD_OFST 0 */ #define MC_CMD_FC_IN_DIAG_DDR_SOAK_OP_OFST 4 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_SUB_OP_OFST 8 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START 0x0 /* enum */ #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT 0x1 /* enum */ #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP 0x2 /* enum */ #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR 0x3 /* enum */ /* MC_CMD_FC_IN_DIAG_DDR_SOAK_START msgrequest */ #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_LEN 24 /* MC_CMD_FC_IN_CMD_OFST 0 */ #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_OP_OFST 4 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_SUB_OP_OFST 8 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_BANK_MASK_OFST 12 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_TEST_PATTERN_OFST 16 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_ZEROS 0x0 /* enum */ #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_ONES 0x1 /* enum */ #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_TEST_TYPE_OFST 20 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_ONGOING_TEST 0x0 /* enum */ #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_SINGLE_TEST 0x1 /* enum */ /* MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT msgrequest */ #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_LEN 16 /* MC_CMD_FC_IN_CMD_OFST 0 */ #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_OP_OFST 4 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_SUB_OP_OFST 8 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_BANK_ID_OFST 12 #define MC_CMD_FC_DDR_BANK0 0x0 /* enum */ #define MC_CMD_FC_DDR_BANK1 0x1 /* enum */ #define MC_CMD_FC_DDR_BANK2 0x2 /* enum */ #define MC_CMD_FC_DDR_BANK3 0x3 /* enum */ #define MC_CMD_FC_DDR_AOEMEM_MAX_BANKS 0x4 /* enum */ /* MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP msgrequest */ #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_LEN 16 /* MC_CMD_FC_IN_CMD_OFST 0 */ #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_OP_OFST 4 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_SUB_OP_OFST 8 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_BANK_MASK_OFST 12 /* MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR msgrequest */ #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_LEN 20 /* MC_CMD_FC_IN_CMD_OFST 0 */ #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_OP_OFST 4 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_SUB_OP_OFST 8 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_BANK_MASK_OFST 12 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_FLAG_ACTION_OFST 16 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_CLEAR 0x0 /* enum */ #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_SET 0x1 /* enum */ /* MC_CMD_FC_IN_DIAG_DATAPATH_CTRL msgrequest */ #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_LEN 12 /* MC_CMD_FC_IN_CMD_OFST 0 */ #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_OP_OFST 4 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SUB_OP_OFST 8 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE 0x0 /* enum */ #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG 0x1 /* enum */ /* MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE msgrequest */ #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_LEN 16 /* MC_CMD_FC_IN_CMD_OFST 0 */ #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_OP_OFST 4 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_SUB_OP_OFST 8 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_MODE_OFST 12 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_PASSTHROUGH 0x0 /* enum */ #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_SNAKE 0x1 /* enum */ /* MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG msgrequest */ #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_LEN 24 /* MC_CMD_FC_IN_CMD_OFST 0 */ #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_OP_OFST 4 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_SUB_OP_OFST 8 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL1_OFST 12 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL2_OFST 16 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL3_OFST 20 /* MC_CMD_FC_OUT msgresponse */ #define MC_CMD_FC_OUT_LEN 0 /* MC_CMD_FC_OUT_NULL msgresponse */ #define MC_CMD_FC_OUT_NULL_LEN 0 /* MC_CMD_FC_OUT_READ32 msgresponse */ #define MC_CMD_FC_OUT_READ32_LENMIN 4 #define MC_CMD_FC_OUT_READ32_LENMAX 252 #define MC_CMD_FC_OUT_READ32_LEN(num) (0+4*(num)) #define MC_CMD_FC_OUT_READ32_BUFFER_OFST 0 #define MC_CMD_FC_OUT_READ32_BUFFER_LEN 4 #define MC_CMD_FC_OUT_READ32_BUFFER_MINNUM 1 #define MC_CMD_FC_OUT_READ32_BUFFER_MAXNUM 63 /* MC_CMD_FC_OUT_WRITE32 msgresponse */ #define MC_CMD_FC_OUT_WRITE32_LEN 0 /* MC_CMD_FC_OUT_TRC_READ msgresponse */ #define MC_CMD_FC_OUT_TRC_READ_LEN 16 #define MC_CMD_FC_OUT_TRC_READ_DATA_OFST 0 #define MC_CMD_FC_OUT_TRC_READ_DATA_LEN 4 #define MC_CMD_FC_OUT_TRC_READ_DATA_NUM 4 /* MC_CMD_FC_OUT_TRC_WRITE msgresponse */ #define MC_CMD_FC_OUT_TRC_WRITE_LEN 0 /* MC_CMD_FC_OUT_GET_VERSION msgresponse */ #define MC_CMD_FC_OUT_GET_VERSION_LEN 12 #define MC_CMD_FC_OUT_GET_VERSION_FIRMWARE_OFST 0 #define MC_CMD_FC_OUT_GET_VERSION_VERSION_OFST 4 #define MC_CMD_FC_OUT_GET_VERSION_VERSION_LEN 8 #define MC_CMD_FC_OUT_GET_VERSION_VERSION_LO_OFST 4 #define MC_CMD_FC_OUT_GET_VERSION_VERSION_HI_OFST 8 /* MC_CMD_FC_OUT_TRC_RX_READ msgresponse */ #define MC_CMD_FC_OUT_TRC_RX_READ_LEN 8 #define MC_CMD_FC_OUT_TRC_RX_READ_DATA_OFST 0 #define MC_CMD_FC_OUT_TRC_RX_READ_DATA_LEN 4 #define MC_CMD_FC_OUT_TRC_RX_READ_DATA_NUM 2 /* MC_CMD_FC_OUT_TRC_RX_WRITE msgresponse */ #define MC_CMD_FC_OUT_TRC_RX_WRITE_LEN 0 /* MC_CMD_FC_OUT_MAC_RECONFIGURE msgresponse */ #define MC_CMD_FC_OUT_MAC_RECONFIGURE_LEN 0 /* MC_CMD_FC_OUT_MAC_SET_LINK msgresponse */ #define MC_CMD_FC_OUT_MAC_SET_LINK_LEN 0 /* MC_CMD_FC_OUT_MAC_READ_STATUS msgresponse */ #define MC_CMD_FC_OUT_MAC_READ_STATUS_LEN 4 #define MC_CMD_FC_OUT_MAC_READ_STATUS_STATUS_OFST 0 /* MC_CMD_FC_OUT_MAC_GET_RX_STATS msgresponse */ #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_LEN ((((0-1+(64*MC_CMD_FC_MAC_RX_NSTATS))+1))>>3) #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_OFST 0 #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_LEN 8 #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_LO_OFST 0 #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_HI_OFST 4 #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_NUM MC_CMD_FC_MAC_RX_NSTATS #define MC_CMD_FC_MAC_RX_STATS_OCTETS 0x0 /* enum */ #define MC_CMD_FC_MAC_RX_OCTETS_OK 0x1 /* enum */ #define MC_CMD_FC_MAC_RX_ALIGNMENT_ERRORS 0x2 /* enum */ #define MC_CMD_FC_MAC_RX_PAUSE_MAC_CTRL_FRAMES 0x3 /* enum */ #define MC_CMD_FC_MAC_RX_FRAMES_OK 0x4 /* enum */ #define MC_CMD_FC_MAC_RX_CRC_ERRORS 0x5 /* enum */ #define MC_CMD_FC_MAC_RX_VLAN_OK 0x6 /* enum */ #define MC_CMD_FC_MAC_RX_ERRORS 0x7 /* enum */ #define MC_CMD_FC_MAC_RX_UCAST_PKTS 0x8 /* enum */ #define MC_CMD_FC_MAC_RX_MULTICAST_PKTS 0x9 /* enum */ #define MC_CMD_FC_MAC_RX_BROADCAST_PKTS 0xa /* enum */ #define MC_CMD_FC_MAC_RX_STATS_DROP_EVENTS 0xb /* enum */ #define MC_CMD_FC_MAC_RX_STATS_PKTS 0xc /* enum */ #define MC_CMD_FC_MAC_RX_STATS_UNDERSIZE_PKTS 0xd /* enum */ #define MC_CMD_FC_MAC_RX_STATS_PKTS_64 0xe /* enum */ #define MC_CMD_FC_MAC_RX_STATS_PKTS_65_127 0xf /* enum */ #define MC_CMD_FC_MAC_RX_STATS_PKTS_128_255 0x10 /* enum */ #define MC_CMD_FC_MAC_RX_STATS_PKTS_256_511 0x11 /* enum */ #define MC_CMD_FC_MAC_RX_STATS_PKTS_512_1023 0x12 /* enum */ #define MC_CMD_FC_MAC_RX_STATS_PKTS_1024_1518 0x13 /* enum */ #define MC_CMD_FC_MAC_RX_STATS_PKTS_1519_MAX 0x14 /* enum */ #define MC_CMD_FC_MAC_RX_STATS_OVERSIZE_PKTS 0x15 /* enum */ #define MC_CMD_FC_MAC_RX_STATS_JABBERS 0x16 /* enum */ #define MC_CMD_FC_MAC_RX_STATS_FRAGMENTS 0x17 /* enum */ #define MC_CMD_FC_MAC_RX_MAC_CONTROL_FRAMES 0x18 /* enum */ #define MC_CMD_FC_MAC_RX_NSTATS 0x19 /* enum */ /* MC_CMD_FC_OUT_MAC_GET_TX_STATS msgresponse */ #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_LEN ((((0-1+(64*MC_CMD_FC_MAC_TX_NSTATS))+1))>>3) #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_OFST 0 #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_LEN 8 #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_LO_OFST 0 #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_HI_OFST 4 #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_NUM MC_CMD_FC_MAC_TX_NSTATS #define MC_CMD_FC_MAC_TX_STATS_OCTETS 0x0 /* enum */ #define MC_CMD_FC_MAC_TX_OCTETS_OK 0x1 /* enum */ #define MC_CMD_FC_MAC_TX_ALIGNMENT_ERRORS 0x2 /* enum */ #define MC_CMD_FC_MAC_TX_PAUSE_MAC_CTRL_FRAMES 0x3 /* enum */ #define MC_CMD_FC_MAC_TX_FRAMES_OK 0x4 /* enum */ #define MC_CMD_FC_MAC_TX_CRC_ERRORS 0x5 /* enum */ #define MC_CMD_FC_MAC_TX_VLAN_OK 0x6 /* enum */ #define MC_CMD_FC_MAC_TX_ERRORS 0x7 /* enum */ #define MC_CMD_FC_MAC_TX_UCAST_PKTS 0x8 /* enum */ #define MC_CMD_FC_MAC_TX_MULTICAST_PKTS 0x9 /* enum */ #define MC_CMD_FC_MAC_TX_BROADCAST_PKTS 0xa /* enum */ #define MC_CMD_FC_MAC_TX_STATS_DROP_EVENTS 0xb /* enum */ #define MC_CMD_FC_MAC_TX_STATS_PKTS 0xc /* enum */ #define MC_CMD_FC_MAC_TX_STATS_UNDERSIZE_PKTS 0xd /* enum */ #define MC_CMD_FC_MAC_TX_STATS_PKTS_64 0xe /* enum */ #define MC_CMD_FC_MAC_TX_STATS_PKTS_65_127 0xf /* enum */ #define MC_CMD_FC_MAC_TX_STATS_PKTS_128_255 0x10 /* enum */ #define MC_CMD_FC_MAC_TX_STATS_PKTS_256_511 0x11 /* enum */ #define MC_CMD_FC_MAC_TX_STATS_PKTS_512_1023 0x12 /* enum */ #define MC_CMD_FC_MAC_TX_STATS_PKTS_1024_1518 0x13 /* enum */ #define MC_CMD_FC_MAC_TX_STATS_PKTS_1519_TX_MTU 0x14 /* enum */ #define MC_CMD_FC_MAC_TX_MAC_CONTROL_FRAMES 0x15 /* enum */ #define MC_CMD_FC_MAC_TX_NSTATS 0x16 /* enum */ /* MC_CMD_FC_OUT_MAC_GET_STATS msgresponse */ #define MC_CMD_FC_OUT_MAC_GET_STATS_LEN ((((0-1+(64*MC_CMD_FC_MAC_NSTATS_PER_BLOCK))+1))>>3) #define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_OFST 0 #define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_LEN 8 #define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_LO_OFST 0 #define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_HI_OFST 4 #define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_NUM MC_CMD_FC_MAC_NSTATS_PER_BLOCK /* MC_CMD_FC_OUT_MAC msgresponse */ #define MC_CMD_FC_OUT_MAC_LEN 0 /* MC_CMD_FC_OUT_SFP msgresponse */ #define MC_CMD_FC_OUT_SFP_LEN 0 /* MC_CMD_FC_OUT_DDR_TEST_START msgresponse */ #define MC_CMD_FC_OUT_DDR_TEST_START_LEN 0 /* MC_CMD_FC_OUT_DDR_TEST_POLL msgresponse */ #define MC_CMD_FC_OUT_DDR_TEST_POLL_LEN 8 #define MC_CMD_FC_OUT_DDR_TEST_POLL_STATUS_OFST 0 #define MC_CMD_FC_OUT_DDR_TEST_POLL_CODE_LBN 0 #define MC_CMD_FC_OUT_DDR_TEST_POLL_CODE_WIDTH 8 #define MC_CMD_FC_OP_DDR_TEST_NONE 0x0 /* enum */ #define MC_CMD_FC_OP_DDR_TEST_INPROGRESS 0x1 /* enum */ #define MC_CMD_FC_OP_DDR_TEST_SUCCESS 0x2 /* enum */ #define MC_CMD_FC_OP_DDR_TEST_TIMER_EXPIRED 0x3 /* enum */ #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T0_LBN 11 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T0_WIDTH 1 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T1_LBN 10 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T1_WIDTH 1 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B0_LBN 9 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B0_WIDTH 1 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B1_LBN 8 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B1_WIDTH 1 #define MC_CMD_FC_OUT_DDR_TEST_POLL_RESULT_OFST 4 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T0_LBN 31 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T0_WIDTH 1 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T1_LBN 30 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T1_WIDTH 1 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B0_LBN 29 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B0_WIDTH 1 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B1_LBN 28 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B1_WIDTH 1 #define MC_CMD_FC_OUT_DDR_TEST_POLL_T0_LBN 15 #define MC_CMD_FC_OUT_DDR_TEST_POLL_T0_WIDTH 5 #define MC_CMD_FC_OUT_DDR_TEST_POLL_T1_LBN 10 #define MC_CMD_FC_OUT_DDR_TEST_POLL_T1_WIDTH 5 #define MC_CMD_FC_OUT_DDR_TEST_POLL_B0_LBN 5 #define MC_CMD_FC_OUT_DDR_TEST_POLL_B0_WIDTH 5 #define MC_CMD_FC_OUT_DDR_TEST_POLL_B1_LBN 0 #define MC_CMD_FC_OUT_DDR_TEST_POLL_B1_WIDTH 5 #define MC_CMD_FC_OUT_DDR_TEST_POLL_TEST_COMPLETE 0x0 /* enum */ #define MC_CMD_FC_OUT_DDR_TEST_POLL_TEST_FAIL 0x1 /* enum */ #define MC_CMD_FC_OUT_DDR_TEST_POLL_TEST_PASS 0x2 /* enum */ #define MC_CMD_FC_OUT_DDR_TEST_POLL_CAL_FAIL 0x3 /* enum */ #define MC_CMD_FC_OUT_DDR_TEST_POLL_CAL_SUCCESS 0x4 /* enum */ /* MC_CMD_FC_OUT_DDR_TEST msgresponse */ #define MC_CMD_FC_OUT_DDR_TEST_LEN 0 /* MC_CMD_FC_OUT_GET_ASSERT msgresponse */ #define MC_CMD_FC_OUT_GET_ASSERT_LEN 144 #define MC_CMD_FC_OUT_GET_ASSERT_GLOBAL_FLAGS_OFST 0 #define MC_CMD_FC_OUT_GET_ASSERT_STATE_LBN 8 #define MC_CMD_FC_OUT_GET_ASSERT_STATE_WIDTH 8 #define MC_CMD_FC_GET_ASSERT_FLAGS_STATE_CLEAR 0x0 /* enum */ #define MC_CMD_FC_GET_ASSERT_FLAGS_STATE_NEW 0x1 /* enum */ #define MC_CMD_FC_GET_ASSERT_FLAGS_STATE_NOTIFIED 0x2 /* enum */ #define MC_CMD_FC_OUT_GET_ASSERT_TYPE_LBN 0 #define MC_CMD_FC_OUT_GET_ASSERT_TYPE_WIDTH 8 #define MC_CMD_FC_GET_ASSERT_FLAGS_TYPE_NONE 0x0 /* enum */ #define MC_CMD_FC_GET_ASSERT_FLAGS_TYPE_EXCEPTION 0x1 /* enum */ #define MC_CMD_FC_GET_ASSERT_FLAGS_TYPE_ASSERTION 0x2 /* enum */ #define MC_CMD_FC_OUT_GET_ASSERT_SAVED_PC_OFFS_OFST 4 #define MC_CMD_FC_OUT_GET_ASSERT_GP_REGS_OFFS_OFST 8 #define MC_CMD_FC_OUT_GET_ASSERT_GP_REGS_OFFS_LEN 4 #define MC_CMD_FC_OUT_GET_ASSERT_GP_REGS_OFFS_NUM 31 #define MC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_TYPE_OFFS_OFST 132 #define MC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_PC_ADDR_OFFS_OFST 136 #define MC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_BAD_ADDR_OFFS_OFST 140 /* MC_CMD_FC_OUT_FPGA_BUILD msgresponse */ #define MC_CMD_FC_OUT_FPGA_BUILD_LEN 32 #define MC_CMD_FC_OUT_FPGA_BUILD_COMPONENT_INFO_OFST 0 #define MC_CMD_FC_OUT_FPGA_BUILD_IS_APPLICATION_LBN 31 #define MC_CMD_FC_OUT_FPGA_BUILD_IS_APPLICATION_WIDTH 1 #define MC_CMD_FC_OUT_FPGA_BUILD_IS_LICENSED_LBN 30 #define MC_CMD_FC_OUT_FPGA_BUILD_IS_LICENSED_WIDTH 1 #define MC_CMD_FC_OUT_FPGA_BUILD_COMPONENT_ID_LBN 16 #define MC_CMD_FC_OUT_FPGA_BUILD_COMPONENT_ID_WIDTH 14 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_MAJOR_LBN 12 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_MAJOR_WIDTH 4 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_MINOR_LBN 4 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_MINOR_WIDTH 8 #define MC_CMD_FC_OUT_FPGA_BUILD_BUILD_NUM_LBN 0 #define MC_CMD_FC_OUT_FPGA_BUILD_BUILD_NUM_WIDTH 4 #define MC_CMD_FC_OUT_FPGA_BUILD_TIMESTAMP_OFST 4 #define MC_CMD_FC_OUT_FPGA_BUILD_PARAMETERS_OFST 8 #define MC_CMD_FC_OUT_FPGA_BUILD_FPGA_TYPE_LBN 0 #define MC_CMD_FC_OUT_FPGA_BUILD_FPGA_TYPE_WIDTH 8 #define MC_CMD_FC_FPGA_TYPE_A7 0xa7 /* enum */ #define MC_CMD_FC_FPGA_TYPE_A5 0xa5 /* enum */ #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED1_LBN 8 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED1_WIDTH 10 #define MC_CMD_FC_OUT_FPGA_BUILD_PTP_ENABLED_LBN 18 #define MC_CMD_FC_OUT_FPGA_BUILD_PTP_ENABLED_WIDTH 1 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM1_RLDRAM_DEF_LBN 19 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM1_RLDRAM_DEF_WIDTH 1 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM2_RLDRAM_DEF_LBN 20 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM2_RLDRAM_DEF_WIDTH 1 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM3_RLDRAM_DEF_LBN 21 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM3_RLDRAM_DEF_WIDTH 1 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM4_RLDRAM_DEF_LBN 22 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM4_RLDRAM_DEF_WIDTH 1 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T0_DDR3_DEF_LBN 23 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T0_DDR3_DEF_WIDTH 1 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_DDR3_DEF_LBN 24 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_DDR3_DEF_WIDTH 1 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B0_DDR3_DEF_LBN 25 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B0_DDR3_DEF_WIDTH 1 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B1_DDR3_DEF_LBN 26 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B1_DDR3_DEF_WIDTH 1 #define MC_CMD_FC_OUT_FPGA_BUILD_DDR3_ECC_ENABLED_LBN 27 #define MC_CMD_FC_OUT_FPGA_BUILD_DDR3_ECC_ENABLED_WIDTH 1 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_QDR_DEF_LBN 28 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_QDR_DEF_WIDTH 1 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED2_LBN 29 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED2_WIDTH 2 #define MC_CMD_FC_OUT_FPGA_BUILD_CRC_APPEND_LBN 31 #define MC_CMD_FC_OUT_FPGA_BUILD_CRC_APPEND_WIDTH 1 #define MC_CMD_FC_OUT_FPGA_BUILD_IDENTIFIER_OFST 12 #define MC_CMD_FC_OUT_FPGA_BUILD_CHANGESET_LBN 0 #define MC_CMD_FC_OUT_FPGA_BUILD_CHANGESET_WIDTH 16 #define MC_CMD_FC_OUT_FPGA_BUILD_BUILD_FLAG_LBN 16 #define MC_CMD_FC_OUT_FPGA_BUILD_BUILD_FLAG_WIDTH 1 #define MC_CMD_FC_FPGA_BUILD_FLAG_INTERNAL 0x0 /* enum */ #define MC_CMD_FC_FPGA_BUILD_FLAG_RELEASE 0x1 /* enum */ #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED3_LBN 17 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED3_WIDTH 15 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_HI_OFST 16 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MINOR_LBN 0 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MINOR_WIDTH 16 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MAJOR_LBN 16 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MAJOR_WIDTH 16 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_LO_OFST 20 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_BUILD_LBN 0 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_BUILD_WIDTH 16 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MICRO_LBN 16 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MICRO_WIDTH 16 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_OFST 16 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_LEN 8 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_LO_OFST 16 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_HI_OFST 20 #define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_LO_OFST 24 #define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_HI_OFST 28 #define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_HIGH_LBN 0 #define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_HIGH_WIDTH 16 /* MC_CMD_FC_OUT_FPGA_SERVICES msgresponse */ #define MC_CMD_FC_OUT_FPGA_SERVICES_LEN 32 #define MC_CMD_FC_OUT_FPGA_SERVICES_COMPONENT_INFO_OFST 0 #define MC_CMD_FC_OUT_FPGA_SERVICES_IS_APPLICATION_LBN 31 #define MC_CMD_FC_OUT_FPGA_SERVICES_IS_APPLICATION_WIDTH 1 #define MC_CMD_FC_OUT_FPGA_SERVICES_IS_LICENSED_LBN 30 #define MC_CMD_FC_OUT_FPGA_SERVICES_IS_LICENSED_WIDTH 1 #define MC_CMD_FC_OUT_FPGA_SERVICES_COMPONENT_ID_LBN 16 #define MC_CMD_FC_OUT_FPGA_SERVICES_COMPONENT_ID_WIDTH 14 #define MC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MAJOR_LBN 12 #define MC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MAJOR_WIDTH 4 #define MC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MINOR_LBN 4 #define MC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MINOR_WIDTH 8 #define MC_CMD_FC_OUT_FPGA_SERVICES_BUILD_NUM_LBN 0 #define MC_CMD_FC_OUT_FPGA_SERVICES_BUILD_NUM_WIDTH 4 #define MC_CMD_FC_OUT_FPGA_SERVICES_TIMESTAMP_OFST 4 #define MC_CMD_FC_OUT_FPGA_SERVICES_PARAMETERS_OFST 8 #define MC_CMD_FC_OUT_FPGA_SERVICES_FC_FLASH_BOOTED_LBN 8 #define MC_CMD_FC_OUT_FPGA_SERVICES_FC_FLASH_BOOTED_WIDTH 1 #define MC_CMD_FC_OUT_FPGA_SERVICES_NIC0_DEF_LBN 27 #define MC_CMD_FC_OUT_FPGA_SERVICES_NIC0_DEF_WIDTH 1 #define MC_CMD_FC_OUT_FPGA_SERVICES_NIC1_DEF_LBN 28 #define MC_CMD_FC_OUT_FPGA_SERVICES_NIC1_DEF_WIDTH 1 #define MC_CMD_FC_OUT_FPGA_SERVICES_SFP0_DEF_LBN 29 #define MC_CMD_FC_OUT_FPGA_SERVICES_SFP0_DEF_WIDTH 1 #define MC_CMD_FC_OUT_FPGA_SERVICES_SFP1_DEF_LBN 30 #define MC_CMD_FC_OUT_FPGA_SERVICES_SFP1_DEF_WIDTH 1 #define MC_CMD_FC_OUT_FPGA_SERVICES_RESERVED_LBN 31 #define MC_CMD_FC_OUT_FPGA_SERVICES_RESERVED_WIDTH 1 #define MC_CMD_FC_OUT_FPGA_SERVICES_IDENTIFIER_OFST 12 #define MC_CMD_FC_OUT_FPGA_SERVICES_CHANGESET_LBN 0 #define MC_CMD_FC_OUT_FPGA_SERVICES_CHANGESET_WIDTH 16 #define MC_CMD_FC_OUT_FPGA_SERVICES_BUILD_FLAG_LBN 16 #define MC_CMD_FC_OUT_FPGA_SERVICES_BUILD_FLAG_WIDTH 1 #define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_OFST 16 #define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_WIDTH_LBN 0 #define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_WIDTH_WIDTH 16 #define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_COUNT_LBN 16 #define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_COUNT_WIDTH 16 #define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_OFST 20 #define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_WIDTH_LBN 0 #define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_WIDTH_WIDTH 16 #define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_COUNT_LBN 16 #define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_COUNT_WIDTH 16 #define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_LO_OFST 24 #define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_HI_OFST 28 #define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_HIGH_LBN 0 #define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_HIGH_WIDTH 16 /* MC_CMD_FC_OUT_BSP_VERSION msgresponse */ #define MC_CMD_FC_OUT_BSP_VERSION_LEN 4 #define MC_CMD_FC_OUT_BSP_VERSION_SYSID_OFST 0 #define MC_CMD_FC_OUT_BSP_VERSION_VERSION_MAJOR_LBN 12 #define MC_CMD_FC_OUT_BSP_VERSION_VERSION_MAJOR_WIDTH 4 #define MC_CMD_FC_OUT_BSP_VERSION_VERSION_MINOR_LBN 4 #define MC_CMD_FC_OUT_BSP_VERSION_VERSION_MINOR_WIDTH 8 #define MC_CMD_FC_OUT_BSP_VERSION_BUILD_NUM_LBN 0 #define MC_CMD_FC_OUT_BSP_VERSION_BUILD_NUM_WIDTH 4 /* MC_CMD_FC_OUT_READ_MAP_COUNT msgresponse */ #define MC_CMD_FC_OUT_READ_MAP_COUNT_LEN 4 #define MC_CMD_FC_OUT_READ_MAP_COUNT_NUM_MAPS_OFST 0 /* MC_CMD_FC_OUT_READ_MAP_INDEX msgresponse */ #define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN 164 #define MC_CMD_FC_OUT_READ_MAP_INDEX_INDEX_OFST 0 #define MC_CMD_FC_OUT_READ_MAP_INDEX_OPTIONS_OFST 4 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_8 0x0 /* enum */ #define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_16 0x1 /* enum */ #define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_32 0x2 /* enum */ #define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_64 0x3 /* enum */ #define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_MASK 0x3 /* enum */ #define MC_CMD_FC_OUT_READ_MAP_INDEX_PATH_FC 0x4 /* enum */ #define MC_CMD_FC_OUT_READ_MAP_INDEX_PATH_MEM 0x8 /* enum */ #define MC_CMD_FC_OUT_READ_MAP_INDEX_PERM_READ 0x10 /* enum */ #define MC_CMD_FC_OUT_READ_MAP_INDEX_PERM_WRITE 0x20 /* enum */ #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_FREE 0x0 /* enum */ #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_LICENSED 0x40 /* enum */ #define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_OFST 8 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_LEN 8 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_LO_OFST 8 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_HI_OFST 12 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_OFST 16 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_LEN 8 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_LO_OFST 16 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_HI_OFST 20 #define MC_CMD_FC_OUT_READ_MAP_INDEX_COMP_INFO_OFST 24 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_OFST 28 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_LEN 8 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_LO_OFST 28 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_HI_OFST 32 #define MC_CMD_FC_OUT_READ_MAP_INDEX_NAME_OFST 36 #define MC_CMD_FC_OUT_READ_MAP_INDEX_NAME_LEN 1 #define MC_CMD_FC_OUT_READ_MAP_INDEX_NAME_NUM 128 /* MC_CMD_FC_OUT_READ_MAP msgresponse */ #define MC_CMD_FC_OUT_READ_MAP_LEN 0 /* MC_CMD_FC_OUT_CAPABILITIES msgresponse */ #define MC_CMD_FC_OUT_CAPABILITIES_LEN 8 #define MC_CMD_FC_OUT_CAPABILITIES_INTERNAL_OFST 0 #define MC_CMD_FC_OUT_CAPABILITIES_EXTERNAL_OFST 4 /* MC_CMD_FC_OUT_GLOBAL_FLAGS msgresponse */ #define MC_CMD_FC_OUT_GLOBAL_FLAGS_LEN 4 #define MC_CMD_FC_OUT_GLOBAL_FLAGS_FLAGS_OFST 0 /* MC_CMD_FC_OUT_IO_REL msgresponse */ #define MC_CMD_FC_OUT_IO_REL_LEN 0 /* MC_CMD_FC_OUT_IO_REL_GET_ADDR msgresponse */ #define MC_CMD_FC_OUT_IO_REL_GET_ADDR_LEN 8 #define MC_CMD_FC_OUT_IO_REL_GET_ADDR_ADDR_HI_OFST 0 #define MC_CMD_FC_OUT_IO_REL_GET_ADDR_ADDR_LO_OFST 4 /* MC_CMD_FC_OUT_IO_REL_READ32 msgresponse */ #define MC_CMD_FC_OUT_IO_REL_READ32_LENMIN 4 #define MC_CMD_FC_OUT_IO_REL_READ32_LENMAX 252 #define MC_CMD_FC_OUT_IO_REL_READ32_LEN(num) (0+4*(num)) #define MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_OFST 0 #define MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_LEN 4 #define MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_MINNUM 1 #define MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_MAXNUM 63 /* MC_CMD_FC_OUT_IO_REL_WRITE32 msgresponse */ #define MC_CMD_FC_OUT_IO_REL_WRITE32_LEN 0 /* MC_CMD_FC_OUT_UHLINK_PHY msgresponse */ #define MC_CMD_FC_OUT_UHLINK_PHY_LEN 48 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_SETTINGS_0_OFST 0 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_VOD_LBN 0 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_VOD_WIDTH 16 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_1STPOSTTAP_LBN 16 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_1STPOSTTAP_WIDTH 16 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_SETTINGS_1_OFST 4 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_PRETAP_LBN 0 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_PRETAP_WIDTH 16 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_2NDPOSTTAP_LBN 16 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_2NDPOSTTAP_WIDTH 16 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_SETTINGS_OFST 8 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_DC_GAIN_LBN 0 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_DC_GAIN_WIDTH 16 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_EQ_CONTROL_LBN 16 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_EQ_CONTROL_WIDTH 16 #define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_OFST 12 #define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_WIDTH_LBN 0 #define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_WIDTH_WIDTH 16 #define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_HEIGHT_LBN 16 #define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_HEIGHT_WIDTH 16 #define MC_CMD_FC_OUT_UHLINK_PHY_PCS_STATUS_OFST 16 #define MC_CMD_FC_OUT_UHLINK_PHY_LINK_STATE_WORD_OFST 20 #define MC_CMD_FC_OUT_UHLINK_PHY_LINK_STATE_LBN 0 #define MC_CMD_FC_OUT_UHLINK_PHY_LINK_STATE_WIDTH 1 #define MC_CMD_FC_OUT_UHLINK_PHY_LINK_CONFIGURED_LBN 1 #define MC_CMD_FC_OUT_UHLINK_PHY_LINK_CONFIGURED_WIDTH 1 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_PARAMS_OFST 24 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_PARAMS_LEN 20 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_SPEED_OFST 24 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_COPPER_LEN_OFST 28 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_DUAL_SPEED_OFST 32 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_PRESENT_OFST 36 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_TYPE_OFST 40 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_OFST 44 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_DFE_LBN 0 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_DFE_WIDTH 1 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_AEQ_LBN 1 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_AEQ_WIDTH 1 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_RX_TUNING_LBN 2 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_RX_TUNING_WIDTH 1 /* MC_CMD_FC_OUT_UHLINK_MAC msgresponse */ #define MC_CMD_FC_OUT_UHLINK_MAC_LEN 20 #define MC_CMD_FC_OUT_UHLINK_MAC_CONFIG_OFST 0 #define MC_CMD_FC_OUT_UHLINK_MAC_MTU_OFST 4 #define MC_CMD_FC_OUT_UHLINK_MAC_IF_STATUS_OFST 8 #define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_OFST 12 #define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_LEN 8 #define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_LO_OFST 12 #define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_HI_OFST 16 /* MC_CMD_FC_OUT_UHLINK_RX_EYE msgresponse */ #define MC_CMD_FC_OUT_UHLINK_RX_EYE_LEN ((((0-1+(32*MC_CMD_FC_UHLINK_RX_EYE_PER_BLOCK))+1))>>3) #define MC_CMD_FC_OUT_UHLINK_RX_EYE_RX_EYE_OFST 0 #define MC_CMD_FC_OUT_UHLINK_RX_EYE_RX_EYE_LEN 4 #define MC_CMD_FC_OUT_UHLINK_RX_EYE_RX_EYE_NUM MC_CMD_FC_UHLINK_RX_EYE_PER_BLOCK /* MC_CMD_FC_OUT_UHLINK_DUMP_RX_EYE_PLOT msgresponse */ #define MC_CMD_FC_OUT_UHLINK_DUMP_RX_EYE_PLOT_LEN 0 /* MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT msgresponse */ #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_LEN ((((32-1+(64*MC_CMD_FC_UHLINK_RX_EYE_PLOT_ROWS_PER_BLOCK))+1))>>3) #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_VALID_OFST 0 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_OFST 4 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_LEN 8 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_LO_OFST 4 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_HI_OFST 8 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_NUM MC_CMD_FC_UHLINK_RX_EYE_PLOT_ROWS_PER_BLOCK /* MC_CMD_FC_OUT_UHLINK_RX_TUNE msgresponse */ #define MC_CMD_FC_OUT_UHLINK_RX_TUNE_LEN 0 /* MC_CMD_FC_OUT_UHLINK_LOOPBACK_SET msgresponse */ #define MC_CMD_FC_OUT_UHLINK_LOOPBACK_SET_LEN 0 /* MC_CMD_FC_OUT_UHLINK_LOOPBACK_GET msgresponse */ #define MC_CMD_FC_OUT_UHLINK_LOOPBACK_GET_LEN 4 #define MC_CMD_FC_OUT_UHLINK_LOOPBACK_GET_STATE_OFST 0 /* MC_CMD_FC_OUT_UHLINK msgresponse */ #define MC_CMD_FC_OUT_UHLINK_LEN 0 /* MC_CMD_FC_OUT_SET_LINK msgresponse */ #define MC_CMD_FC_OUT_SET_LINK_LEN 0 /* MC_CMD_FC_OUT_LICENSE msgresponse */ #define MC_CMD_FC_OUT_LICENSE_LEN 12 #define MC_CMD_FC_OUT_LICENSE_VALID_KEYS_OFST 0 #define MC_CMD_FC_OUT_LICENSE_INVALID_KEYS_OFST 4 #define MC_CMD_FC_OUT_LICENSE_BLACKLISTED_KEYS_OFST 8 /* MC_CMD_FC_OUT_STARTUP msgresponse */ #define MC_CMD_FC_OUT_STARTUP_LEN 4 #define MC_CMD_FC_OUT_STARTUP_CAPABILITIES_OFST 0 #define MC_CMD_FC_OUT_STARTUP_CAN_ACCESS_FLASH_LBN 0 #define MC_CMD_FC_OUT_STARTUP_CAN_ACCESS_FLASH_WIDTH 1 /* MC_CMD_FC_OUT_DMA_READ msgresponse */ #define MC_CMD_FC_OUT_DMA_READ_LENMIN 1 #define MC_CMD_FC_OUT_DMA_READ_LENMAX 252 #define MC_CMD_FC_OUT_DMA_READ_LEN(num) (0+1*(num)) #define MC_CMD_FC_OUT_DMA_READ_DATA_OFST 0 #define MC_CMD_FC_OUT_DMA_READ_DATA_LEN 1 #define MC_CMD_FC_OUT_DMA_READ_DATA_MINNUM 1 #define MC_CMD_FC_OUT_DMA_READ_DATA_MAXNUM 252 /* MC_CMD_FC_OUT_TIMED_READ_SET msgresponse */ #define MC_CMD_FC_OUT_TIMED_READ_SET_LEN 4 #define MC_CMD_FC_OUT_TIMED_READ_SET_FC_HANDLE_OFST 0 /* MC_CMD_FC_OUT_TIMED_READ_GET msgresponse */ #define MC_CMD_FC_OUT_TIMED_READ_GET_LEN 52 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_HANDLE_OFST 0 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_OFST 4 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_LEN 8 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_LO_OFST 4 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_HI_OFST 8 #define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_OFST 12 #define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_LEN 8 #define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_LO_OFST 12 #define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_HI_OFST 16 #define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_LENGTH_OFST 20 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_LENGTH_OFST 24 #define MC_CMD_FC_OUT_TIMED_READ_GET_FLAGS_OFST 28 #define MC_CMD_FC_OUT_TIMED_READ_GET_PERIOD_OFST 32 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_OFST 36 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_LEN 8 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_LO_OFST 36 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_HI_OFST 40 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_OFST 44 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_LEN 8 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_LO_OFST 44 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_HI_OFST 48 /* MC_CMD_FC_OUT_LOG_ADDR_RANGE msgresponse */ #define MC_CMD_FC_OUT_LOG_ADDR_RANGE_LEN 0 /* MC_CMD_FC_OUT_LOG msgresponse */ #define MC_CMD_FC_OUT_LOG_LEN 0 /* MC_CMD_FC_OUT_CLOCK_GET_TIME msgresponse */ #define MC_CMD_FC_OUT_CLOCK_GET_TIME_LEN 24 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_CLOCK_ID_OFST 0 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_OFST 4 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_LEN 8 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_LO_OFST 4 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_HI_OFST 8 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_NANOSECONDS_OFST 12 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_RANGE_OFST 16 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_PRECISION_OFST 20 /* MC_CMD_FC_OUT_CLOCK_SET_TIME msgresponse */ #define MC_CMD_FC_OUT_CLOCK_SET_TIME_LEN 0 /* MC_CMD_FC_OUT_DDR_SET_SPD msgresponse */ #define MC_CMD_FC_OUT_DDR_SET_SPD_LEN 0 /* MC_CMD_FC_OUT_DDR_GET_STATUS msgresponse */ #define MC_CMD_FC_OUT_DDR_GET_STATUS_LEN 4 #define MC_CMD_FC_OUT_DDR_GET_STATUS_FLAGS_OFST 0 #define MC_CMD_FC_OUT_DDR_GET_STATUS_READY_LBN 0 #define MC_CMD_FC_OUT_DDR_GET_STATUS_READY_WIDTH 1 #define MC_CMD_FC_OUT_DDR_GET_STATUS_CALIBRATED_LBN 1 #define MC_CMD_FC_OUT_DDR_GET_STATUS_CALIBRATED_WIDTH 1 /* MC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT msgresponse */ #define MC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT_LEN 8 #define MC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT_SECONDS_OFST 0 #define MC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT_NANOSECONDS_OFST 4 /* MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT msgresponse */ #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_LENMIN 8 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_LENMAX 248 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_LEN(num) (0+8*(num)) #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_SECONDS_OFST 0 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_NANOSECONDS_OFST 4 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_OFST 0 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_LEN 8 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_LO_OFST 0 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_HI_OFST 4 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_MINNUM 0 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_MAXNUM 31 /* MC_CMD_FC_OUT_SPI_READ msgresponse */ #define MC_CMD_FC_OUT_SPI_READ_LENMIN 4 #define MC_CMD_FC_OUT_SPI_READ_LENMAX 252 #define MC_CMD_FC_OUT_SPI_READ_LEN(num) (0+4*(num)) #define MC_CMD_FC_OUT_SPI_READ_BUFFER_OFST 0 #define MC_CMD_FC_OUT_SPI_READ_BUFFER_LEN 4 #define MC_CMD_FC_OUT_SPI_READ_BUFFER_MINNUM 1 #define MC_CMD_FC_OUT_SPI_READ_BUFFER_MAXNUM 63 /* MC_CMD_FC_OUT_SPI_WRITE msgresponse */ #define MC_CMD_FC_OUT_SPI_WRITE_LEN 0 /* MC_CMD_FC_OUT_SPI_ERASE msgresponse */ #define MC_CMD_FC_OUT_SPI_ERASE_LEN 0 /* MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG msgresponse */ #define MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG_LEN 8 #define MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG_TOGGLE_COUNT_OFST 0 #define MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG_CLKEN_COUNT_OFST 4 /* MC_CMD_FC_OUT_DIAG_POWER_NOISE_WRITE_CONFIG msgresponse */ #define MC_CMD_FC_OUT_DIAG_POWER_NOISE_WRITE_CONFIG_LEN 0 /* MC_CMD_FC_OUT_DIAG_DDR_SOAK_START msgresponse */ #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_START_LEN 0 /* MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT msgresponse */ #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_LEN 8 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_STATUS_OFST 0 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PASSED_LBN 0 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PASSED_WIDTH 1 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_FAILED_LBN 1 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_FAILED_WIDTH 1 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_COMPLETED_LBN 2 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_COMPLETED_WIDTH 1 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_TIMEOUT_LBN 3 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_TIMEOUT_WIDTH 1 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PNF_LBN 4 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PNF_WIDTH 1 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_ERR_COUNT_OFST 4 /* MC_CMD_FC_OUT_DIAG_DDR_SOAK_STOP msgresponse */ #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_STOP_LEN 0 /* MC_CMD_FC_OUT_DIAG_DDR_SOAK_ERROR msgresponse */ #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_ERROR_LEN 0 /* MC_CMD_FC_OUT_DIAG_DATAPATH_CTRL_SET_MODE msgresponse */ #define MC_CMD_FC_OUT_DIAG_DATAPATH_CTRL_SET_MODE_LEN 0 /* MC_CMD_FC_OUT_DIAG_DATAPATH_CTRL_RAW_CONFIG msgresponse */ #define MC_CMD_FC_OUT_DIAG_DATAPATH_CTRL_RAW_CONFIG_LEN 0 /***********************************/ /* MC_CMD_AOE * AOE operations (on MC rather than FC) */ #define MC_CMD_AOE 0xa /* MC_CMD_AOE_IN msgrequest */ #define MC_CMD_AOE_IN_LEN 4 #define MC_CMD_AOE_IN_OP_HDR_OFST 0 #define MC_CMD_AOE_IN_OP_LBN 0 #define MC_CMD_AOE_IN_OP_WIDTH 8 #define MC_CMD_AOE_OP_INFO 0x1 /* enum */ #define MC_CMD_AOE_OP_CURRENTS 0x2 /* enum */ #define MC_CMD_AOE_OP_TEMPERATURES 0x3 /* enum */ #define MC_CMD_AOE_OP_CPLD_IDLE 0x4 /* enum */ #define MC_CMD_AOE_OP_CPLD_READ 0x5 /* enum */ #define MC_CMD_AOE_OP_CPLD_WRITE 0x6 /* enum */ #define MC_CMD_AOE_OP_CPLD_INSTRUCTION 0x7 /* enum */ #define MC_CMD_AOE_OP_CPLD_REPROGRAM 0x8 /* enum */ #define MC_CMD_AOE_OP_POWER 0x9 /* enum */ #define MC_CMD_AOE_OP_LOAD 0xa /* enum */ #define MC_CMD_AOE_OP_FAN_CONTROL 0xb /* enum */ #define MC_CMD_AOE_OP_FAN_FAILURES 0xc /* enum */ #define MC_CMD_AOE_OP_MAC_STATS 0xd /* enum */ #define MC_CMD_AOE_OP_GET_PHY_MEDIA_INFO 0xe /* enum */ #define MC_CMD_AOE_OP_JTAG_WRITE 0xf /* enum */ #define MC_CMD_AOE_OP_FPGA_ACCESS 0x10 /* enum */ #define MC_CMD_AOE_OP_SET_MTU_OFFSET 0x11 /* enum */ #define MC_CMD_AOE_OP_LINK_STATE 0x12 /* enum */ #define MC_CMD_AOE_OP_SIENA_STATS 0x13 /* enum */ #define MC_CMD_AOE_OP_DDR 0x14 /* enum */ #define MC_CMD_AOE_OP_FC 0x15 /* enum */ #define MC_CMD_AOE_OP_DDR_ECC_STATUS 0x16 /* enum */ #define MC_CMD_AOE_OP_MC_SPI_MASTER 0x17 /* enum */ /* MC_CMD_AOE_OUT msgresponse */ #define MC_CMD_AOE_OUT_LEN 0 /* MC_CMD_AOE_IN_INFO msgrequest */ #define MC_CMD_AOE_IN_INFO_LEN 4 #define MC_CMD_AOE_IN_CMD_OFST 0 /* MC_CMD_AOE_IN_CURRENTS msgrequest */ #define MC_CMD_AOE_IN_CURRENTS_LEN 4 /* MC_CMD_AOE_IN_CMD_OFST 0 */ /* MC_CMD_AOE_IN_TEMPERATURES msgrequest */ #define MC_CMD_AOE_IN_TEMPERATURES_LEN 4 /* MC_CMD_AOE_IN_CMD_OFST 0 */ /* MC_CMD_AOE_IN_CPLD_IDLE msgrequest */ #define MC_CMD_AOE_IN_CPLD_IDLE_LEN 4 /* MC_CMD_AOE_IN_CMD_OFST 0 */ /* MC_CMD_AOE_IN_CPLD_READ msgrequest */ #define MC_CMD_AOE_IN_CPLD_READ_LEN 12 /* MC_CMD_AOE_IN_CMD_OFST 0 */ #define MC_CMD_AOE_IN_CPLD_READ_REGISTER_OFST 4 #define MC_CMD_AOE_IN_CPLD_READ_WIDTH_OFST 8 /* MC_CMD_AOE_IN_CPLD_WRITE msgrequest */ #define MC_CMD_AOE_IN_CPLD_WRITE_LEN 16 /* MC_CMD_AOE_IN_CMD_OFST 0 */ #define MC_CMD_AOE_IN_CPLD_WRITE_REGISTER_OFST 4 #define MC_CMD_AOE_IN_CPLD_WRITE_WIDTH_OFST 8 #define MC_CMD_AOE_IN_CPLD_WRITE_VALUE_OFST 12 /* MC_CMD_AOE_IN_CPLD_INSTRUCTION msgrequest */ #define MC_CMD_AOE_IN_CPLD_INSTRUCTION_LEN 8 /* MC_CMD_AOE_IN_CMD_OFST 0 */ #define MC_CMD_AOE_IN_CPLD_INSTRUCTION_INSTRUCTION_OFST 4 /* MC_CMD_AOE_IN_CPLD_REPROGRAM msgrequest */ #define MC_CMD_AOE_IN_CPLD_REPROGRAM_LEN 8 /* MC_CMD_AOE_IN_CMD_OFST 0 */ #define MC_CMD_AOE_IN_CPLD_REPROGRAM_OP_OFST 4 #define MC_CMD_AOE_IN_CPLD_REPROGRAM_REPROGRAM 0x1 /* enum */ #define MC_CMD_AOE_IN_CPLD_REPROGRAM_REPROGRAM_EVENT 0x3 /* enum */ #define MC_CMD_AOE_IN_CPLD_REPROGRAM_STATUS 0x4 /* enum */ /* MC_CMD_AOE_IN_POWER msgrequest */ #define MC_CMD_AOE_IN_POWER_LEN 8 /* MC_CMD_AOE_IN_CMD_OFST 0 */ #define MC_CMD_AOE_IN_POWER_OP_OFST 4 #define MC_CMD_AOE_IN_POWER_OFF 0x0 /* enum */ #define MC_CMD_AOE_IN_POWER_ON 0x1 /* enum */ #define MC_CMD_AOE_IN_POWER_CLEAR 0x2 /* enum */ #define MC_CMD_AOE_IN_POWER_SHOW_CURRENT 0x3 /* enum */ #define MC_CMD_AOE_IN_POWER_SHOW_PEAK 0x4 /* enum */ #define MC_CMD_AOE_IN_POWER_DDR_LAST 0x5 /* enum */ #define MC_CMD_AOE_IN_POWER_DDR_PEAK 0x6 /* enum */ #define MC_CMD_AOE_IN_POWER_DDR_CLEAR 0x7 /* enum */ /* MC_CMD_AOE_IN_LOAD msgrequest */ #define MC_CMD_AOE_IN_LOAD_LEN 8 /* MC_CMD_AOE_IN_CMD_OFST 0 */ #define MC_CMD_AOE_IN_LOAD_IMAGE_OFST 4 /* MC_CMD_AOE_IN_FAN_CONTROL msgrequest */ #define MC_CMD_AOE_IN_FAN_CONTROL_LEN 8 /* MC_CMD_AOE_IN_CMD_OFST 0 */ #define MC_CMD_AOE_IN_FAN_CONTROL_REAL_RPM_OFST 4 /* MC_CMD_AOE_IN_FAN_FAILURES msgrequest */ #define MC_CMD_AOE_IN_FAN_FAILURES_LEN 4 /* MC_CMD_AOE_IN_CMD_OFST 0 */ /* MC_CMD_AOE_IN_MAC_STATS msgrequest */ #define MC_CMD_AOE_IN_MAC_STATS_LEN 24 /* MC_CMD_AOE_IN_CMD_OFST 0 */ #define MC_CMD_AOE_IN_MAC_STATS_PORT_OFST 4 #define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_OFST 8 #define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_LEN 8 #define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_LO_OFST 8 #define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_HI_OFST 12 #define MC_CMD_AOE_IN_MAC_STATS_CMD_OFST 16 #define MC_CMD_AOE_IN_MAC_STATS_DMA_LBN 0 #define MC_CMD_AOE_IN_MAC_STATS_DMA_WIDTH 1 #define MC_CMD_AOE_IN_MAC_STATS_CLEAR_LBN 1 #define MC_CMD_AOE_IN_MAC_STATS_CLEAR_WIDTH 1 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_CHANGE_LBN 2 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_CHANGE_WIDTH 1 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_ENABLE_LBN 3 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_ENABLE_WIDTH 1 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_CLEAR_LBN 4 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_CLEAR_WIDTH 1 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_NOEVENT_LBN 5 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_NOEVENT_WIDTH 1 #define MC_CMD_AOE_IN_MAC_STATS_PERIOD_MS_LBN 16 #define MC_CMD_AOE_IN_MAC_STATS_PERIOD_MS_WIDTH 16 #define MC_CMD_AOE_IN_MAC_STATS_DMA_LEN_OFST 20 /* MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO msgrequest */ #define MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO_LEN 12 /* MC_CMD_AOE_IN_CMD_OFST 0 */ #define MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO_PORT_OFST 4 #define MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO_PAGE_OFST 8 /* MC_CMD_AOE_IN_JTAG_WRITE msgrequest */ #define MC_CMD_AOE_IN_JTAG_WRITE_LENMIN 12 #define MC_CMD_AOE_IN_JTAG_WRITE_LENMAX 252 #define MC_CMD_AOE_IN_JTAG_WRITE_LEN(num) (8+4*(num)) /* MC_CMD_AOE_IN_CMD_OFST 0 */ #define MC_CMD_AOE_IN_JTAG_WRITE_DATALEN_OFST 4 #define MC_CMD_AOE_IN_JTAG_WRITE_DATA_OFST 8 #define MC_CMD_AOE_IN_JTAG_WRITE_DATA_LEN 4 #define MC_CMD_AOE_IN_JTAG_WRITE_DATA_MINNUM 1 #define MC_CMD_AOE_IN_JTAG_WRITE_DATA_MAXNUM 61 /* MC_CMD_AOE_IN_FPGA_ACCESS msgrequest */ #define MC_CMD_AOE_IN_FPGA_ACCESS_LEN 8 /* MC_CMD_AOE_IN_CMD_OFST 0 */ #define MC_CMD_AOE_IN_FPGA_ACCESS_OP_OFST 4 #define MC_CMD_AOE_IN_FPGA_ACCESS_ENABLE 0x1 /* enum */ #define MC_CMD_AOE_IN_FPGA_ACCESS_DISABLE 0x2 /* enum */ /* MC_CMD_AOE_IN_SET_MTU_OFFSET msgrequest */ #define MC_CMD_AOE_IN_SET_MTU_OFFSET_LEN 12 /* MC_CMD_AOE_IN_CMD_OFST 0 */ #define MC_CMD_AOE_IN_SET_MTU_OFFSET_PORT_OFST 4 #define MC_CMD_AOE_IN_SET_MTU_OFFSET_ALL_EXTERNAL 0x8000 /* enum */ #define MC_CMD_AOE_IN_SET_MTU_OFFSET_ALL_INTERNAL 0x4000 /* enum */ #define MC_CMD_AOE_IN_SET_MTU_OFFSET_OFFSET_OFST 8 /* MC_CMD_AOE_IN_LINK_STATE msgrequest */ #define MC_CMD_AOE_IN_LINK_STATE_LEN 8 /* MC_CMD_AOE_IN_CMD_OFST 0 */ #define MC_CMD_AOE_IN_LINK_STATE_MODE_OFST 4 #define MC_CMD_AOE_IN_LINK_STATE_CONFIG_MODE_LBN 0 #define MC_CMD_AOE_IN_LINK_STATE_CONFIG_MODE_WIDTH 8 #define MC_CMD_AOE_IN_LINK_STATE_SIMPLE_SEPARATE 0x0 /* enum */ #define MC_CMD_AOE_IN_LINK_STATE_SIMPLE_COMBINED 0x1 /* enum */ #define MC_CMD_AOE_IN_LINK_STATE_DIAGNOSTIC 0x2 /* enum */ #define MC_CMD_AOE_IN_LINK_STATE_CUSTOM 0x3 /* enum */ #define MC_CMD_AOE_IN_LINK_STATE_OPERATION_LBN 8 #define MC_CMD_AOE_IN_LINK_STATE_OPERATION_WIDTH 8 #define MC_CMD_AOE_IN_LINK_STATE_OP_NONE 0x0 /* enum */ #define MC_CMD_AOE_IN_LINK_STATE_OP_OR 0x1 /* enum */ #define MC_CMD_AOE_IN_LINK_STATE_OP_AND 0x2 /* enum */ #define MC_CMD_AOE_IN_LINK_STATE_SFP_MASK_LBN 16 #define MC_CMD_AOE_IN_LINK_STATE_SFP_MASK_WIDTH 16 /* MC_CMD_AOE_IN_SIENA_STATS msgrequest */ #define MC_CMD_AOE_IN_SIENA_STATS_LEN 8 /* MC_CMD_AOE_IN_CMD_OFST 0 */ #define MC_CMD_AOE_IN_SIENA_STATS_MODE_OFST 4 #define MC_CMD_AOE_IN_SIENA_STATS_STATS_SIENA 0x0 /* enum */ #define MC_CMD_AOE_IN_SIENA_STATS_STATS_AOE 0x1 /* enum */ /* MC_CMD_AOE_IN_DDR msgrequest */ #define MC_CMD_AOE_IN_DDR_LEN 12 /* MC_CMD_AOE_IN_CMD_OFST 0 */ #define MC_CMD_AOE_IN_DDR_BANK_OFST 4 /* Enum values, see field(s): */ /* MC_CMD_FC_IN_DDR_BANK */ #define MC_CMD_AOE_IN_DDR_SPD_PAGE_ID_OFST 8 /* MC_CMD_AOE_IN_FC msgrequest */ #define MC_CMD_AOE_IN_FC_LEN 4 /* MC_CMD_AOE_IN_CMD_OFST 0 */ /* MC_CMD_AOE_IN_DDR_ECC_STATUS msgrequest */ #define MC_CMD_AOE_IN_DDR_ECC_STATUS_LEN 8 /* MC_CMD_AOE_IN_CMD_OFST 0 */ #define MC_CMD_AOE_IN_DDR_ECC_STATUS_BANK_OFST 4 /* Enum values, see field(s): */ /* MC_CMD_FC_IN_DDR_BANK */ /* MC_CMD_AOE_IN_MC_SPI_MASTER msgrequest */ #define MC_CMD_AOE_IN_MC_SPI_MASTER_LEN 8 /* MC_CMD_AOE_IN_CMD_OFST 0 */ #define MC_CMD_AOE_IN_MC_SPI_MASTER_OP_OFST 4 #define MC_CMD_AOE_IN_MC_SPI_MASTER_READ 0x0 /* enum */ #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE 0x1 /* enum */ /* MC_CMD_AOE_IN_MC_SPI_MASTER_READ msgrequest */ #define MC_CMD_AOE_IN_MC_SPI_MASTER_READ_LEN 12 /* MC_CMD_AOE_IN_CMD_OFST 0 */ #define MC_CMD_AOE_IN_MC_SPI_MASTER_READ_OP_OFST 4 #define MC_CMD_AOE_IN_MC_SPI_MASTER_READ_OFFSET_OFST 8 /* MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE msgrequest */ #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_LEN 16 /* MC_CMD_AOE_IN_CMD_OFST 0 */ #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_OP_OFST 4 #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_OFFSET_OFST 8 #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_DATA_OFST 12 /* MC_CMD_AOE_OUT_INFO msgresponse */ #define MC_CMD_AOE_OUT_INFO_LEN 44 #define MC_CMD_AOE_OUT_INFO_CPLD_IDCODE_OFST 0 #define MC_CMD_AOE_OUT_INFO_CPLD_VERSION_OFST 4 #define MC_CMD_AOE_OUT_INFO_FPGA_IDCODE_OFST 8 #define MC_CMD_AOE_OUT_INFO_FPGA_VERSION_OFST 12 #define MC_CMD_AOE_OUT_INFO_FPGA_TYPE_OFST 16 #define MC_CMD_AOE_OUT_INFO_FPGA_STATE_OFST 20 #define MC_CMD_AOE_OUT_INFO_FPGA_IMAGE_OFST 24 #define MC_CMD_AOE_OUT_INFO_FC_STATE_OFST 28 #define MC_CMD_AOE_OUT_INFO_WATCHDOG 0x1 /* enum */ #define MC_CMD_AOE_OUT_INFO_COMMS 0x2 /* enum */ #define MC_CMD_AOE_OUT_INFO_FLAGS_OFST 32 #define MC_CMD_AOE_OUT_INFO_PEG_POWER 0x1 /* enum */ #define MC_CMD_AOE_OUT_INFO_CPLD_GOOD 0x2 /* enum */ #define MC_CMD_AOE_OUT_INFO_FPGA_GOOD 0x4 /* enum */ #define MC_CMD_AOE_OUT_INFO_FPGA_POWER 0x8 /* enum */ #define MC_CMD_AOE_OUT_INFO_BAD_SODIMM 0x10 /* enum */ #define MC_CMD_AOE_OUT_INFO_HAS_BYTEBLASTER 0x20 /* enum */ #define MC_CMD_AOE_OUT_INFO_BOARD_REVISION_OFST 36 #define MC_CMD_AOE_OUT_INFO_UNKNOWN 0x0 /* enum */ #define MC_CMD_AOE_OUT_INFO_R1_0 0x10 /* enum */ #define MC_CMD_AOE_OUT_INFO_R1_1 0x11 /* enum */ #define MC_CMD_AOE_OUT_INFO_R1_2 0x12 /* enum */ #define MC_CMD_AOE_OUT_INFO_FC_BOOT_RESULT_OFST 40 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_NO_ERROR 0x0 /* enum */ #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_ADDRESS 0x1 /* enum */ #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_MAGIC 0x2 /* enum */ #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_TEXT 0x3 /* enum */ #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_CHECKSUM 0x4 /* enum */ #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_BSP 0x5 /* enum */ #define MC_CMD_AOE_OUT_INFO_FC_BOOT_APP_EXECUTE 0x80 /* enum */ #define MC_CMD_AOE_OUT_INFO_FC_BOOT_NO_BOOTROM 0xff /* enum */ /* MC_CMD_AOE_OUT_CURRENTS msgresponse */ #define MC_CMD_AOE_OUT_CURRENTS_LEN 68 #define MC_CMD_AOE_OUT_CURRENTS_VALUES_OFST 0 #define MC_CMD_AOE_OUT_CURRENTS_VALUES_LEN 4 #define MC_CMD_AOE_OUT_CURRENTS_VALUES_NUM 17 #define MC_CMD_AOE_OUT_CURRENTS_I_2V5 0x0 /* enum */ #define MC_CMD_AOE_OUT_CURRENTS_I_1V8 0x1 /* enum */ #define MC_CMD_AOE_OUT_CURRENTS_I_GXB 0x2 /* enum */ #define MC_CMD_AOE_OUT_CURRENTS_I_PGM 0x3 /* enum */ #define MC_CMD_AOE_OUT_CURRENTS_I_XCVR 0x4 /* enum */ #define MC_CMD_AOE_OUT_CURRENTS_I_1V5 0x5 /* enum */ #define MC_CMD_AOE_OUT_CURRENTS_V_3V3 0x6 /* enum */ #define MC_CMD_AOE_OUT_CURRENTS_V_1V5 0x7 /* enum */ #define MC_CMD_AOE_OUT_CURRENTS_I_IN 0x8 /* enum */ #define MC_CMD_AOE_OUT_CURRENTS_I_OUT 0x9 /* enum */ #define MC_CMD_AOE_OUT_CURRENTS_V_IN 0xa /* enum */ #define MC_CMD_AOE_OUT_CURRENTS_I_OUT_DDR1 0xb /* enum */ #define MC_CMD_AOE_OUT_CURRENTS_V_OUT_DDR1 0xc /* enum */ #define MC_CMD_AOE_OUT_CURRENTS_I_OUT_DDR2 0xd /* enum */ #define MC_CMD_AOE_OUT_CURRENTS_V_OUT_DDR2 0xe /* enum */ #define MC_CMD_AOE_OUT_CURRENTS_I_OUT_DDR3 0xf /* enum */ #define MC_CMD_AOE_OUT_CURRENTS_V_OUT_DDR3 0x10 /* enum */ /* MC_CMD_AOE_OUT_TEMPERATURES msgresponse */ #define MC_CMD_AOE_OUT_TEMPERATURES_LEN 40 #define MC_CMD_AOE_OUT_TEMPERATURES_VALUES_OFST 0 #define MC_CMD_AOE_OUT_TEMPERATURES_VALUES_LEN 4 #define MC_CMD_AOE_OUT_TEMPERATURES_VALUES_NUM 10 #define MC_CMD_AOE_OUT_TEMPERATURES_MAIN_0 0x0 /* enum */ #define MC_CMD_AOE_OUT_TEMPERATURES_MAIN_1 0x1 /* enum */ #define MC_CMD_AOE_OUT_TEMPERATURES_IND_0 0x2 /* enum */ #define MC_CMD_AOE_OUT_TEMPERATURES_IND_1 0x3 /* enum */ #define MC_CMD_AOE_OUT_TEMPERATURES_VCCIO1 0x4 /* enum */ #define MC_CMD_AOE_OUT_TEMPERATURES_VCCIO2 0x5 /* enum */ #define MC_CMD_AOE_OUT_TEMPERATURES_VCCIO3 0x6 /* enum */ #define MC_CMD_AOE_OUT_TEMPERATURES_PSU 0x7 /* enum */ #define MC_CMD_AOE_OUT_TEMPERATURES_FPGA 0x8 /* enum */ #define MC_CMD_AOE_OUT_TEMPERATURES_SIENA 0x9 /* enum */ /* MC_CMD_AOE_OUT_CPLD_READ msgresponse */ #define MC_CMD_AOE_OUT_CPLD_READ_LEN 4 #define MC_CMD_AOE_OUT_CPLD_READ_VALUE_OFST 0 /* MC_CMD_AOE_OUT_FAN_FAILURES msgresponse */ #define MC_CMD_AOE_OUT_FAN_FAILURES_LENMIN 4 #define MC_CMD_AOE_OUT_FAN_FAILURES_LENMAX 252 #define MC_CMD_AOE_OUT_FAN_FAILURES_LEN(num) (0+4*(num)) #define MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_OFST 0 #define MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_LEN 4 #define MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_MINNUM 1 #define MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_MAXNUM 63 /* MC_CMD_AOE_OUT_CPLD_REPROGRAM msgresponse */ #define MC_CMD_AOE_OUT_CPLD_REPROGRAM_LEN 4 #define MC_CMD_AOE_OUT_CPLD_REPROGRAM_STATUS_OFST 0 /* MC_CMD_AOE_OUT_MAC_STATS_DMA msgresponse */ #define MC_CMD_AOE_OUT_MAC_STATS_DMA_LEN 0 /* MC_CMD_AOE_OUT_MAC_STATS_NO_DMA msgresponse */ #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_LEN (((MC_CMD_MAC_NSTATS*64))>>3) #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_OFST 0 #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_LEN 8 #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_LO_OFST 0 #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_HI_OFST 4 #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS /* MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO msgresponse */ #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_LENMIN 5 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_LENMAX 252 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_LEN(num) (4+1*(num)) #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATALEN_OFST 0 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_OFST 4 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_LEN 1 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_MINNUM 1 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_MAXNUM 248 /* MC_CMD_AOE_OUT_JTAG_WRITE msgresponse */ #define MC_CMD_AOE_OUT_JTAG_WRITE_LENMIN 12 #define MC_CMD_AOE_OUT_JTAG_WRITE_LENMAX 252 #define MC_CMD_AOE_OUT_JTAG_WRITE_LEN(num) (8+4*(num)) #define MC_CMD_AOE_OUT_JTAG_WRITE_DATALEN_OFST 0 #define MC_CMD_AOE_OUT_JTAG_WRITE_PAD_OFST 4 #define MC_CMD_AOE_OUT_JTAG_WRITE_DATA_OFST 8 #define MC_CMD_AOE_OUT_JTAG_WRITE_DATA_LEN 4 #define MC_CMD_AOE_OUT_JTAG_WRITE_DATA_MINNUM 1 #define MC_CMD_AOE_OUT_JTAG_WRITE_DATA_MAXNUM 61 /* MC_CMD_AOE_OUT_FPGA_ACCESS msgresponse */ #define MC_CMD_AOE_OUT_FPGA_ACCESS_LEN 0 /* MC_CMD_AOE_OUT_DDR msgresponse */ #define MC_CMD_AOE_OUT_DDR_LENMIN 17 #define MC_CMD_AOE_OUT_DDR_LENMAX 252 #define MC_CMD_AOE_OUT_DDR_LEN(num) (16+1*(num)) #define MC_CMD_AOE_OUT_DDR_FLAGS_OFST 0 #define MC_CMD_AOE_OUT_DDR_PRESENT_LBN 0 #define MC_CMD_AOE_OUT_DDR_PRESENT_WIDTH 1 #define MC_CMD_AOE_OUT_DDR_POWERED_LBN 1 #define MC_CMD_AOE_OUT_DDR_POWERED_WIDTH 1 #define MC_CMD_AOE_OUT_DDR_OPERATIONAL_LBN 2 #define MC_CMD_AOE_OUT_DDR_OPERATIONAL_WIDTH 1 #define MC_CMD_AOE_OUT_DDR_CAPACITY_OFST 4 #define MC_CMD_AOE_OUT_DDR_TYPE_OFST 8 #define MC_CMD_AOE_OUT_DDR_VOLTAGE_OFST 12 #define MC_CMD_AOE_OUT_DDR_SPD_OFST 16 #define MC_CMD_AOE_OUT_DDR_SPD_LEN 1 #define MC_CMD_AOE_OUT_DDR_SPD_MINNUM 1 #define MC_CMD_AOE_OUT_DDR_SPD_MAXNUM 236 /* MC_CMD_AOE_OUT_LINK_STATE msgresponse */ #define MC_CMD_AOE_OUT_LINK_STATE_LEN 0 /* MC_CMD_AOE_OUT_FC msgresponse */ #define MC_CMD_AOE_OUT_FC_LEN 0 /* MC_CMD_AOE_OUT_DDR_ECC_STATUS msgresponse */ #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_LEN 8 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_FLAGS_OFST 0 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_VALID_LBN 0 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_VALID_WIDTH 1 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_STATUS_OFST 4 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_LBN 0 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_WIDTH 1 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_LBN 1 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_WIDTH 1 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_LBN 2 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_WIDTH 1 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_COUNT_LBN 8 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_COUNT_WIDTH 8 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_COUNT_LBN 16 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_COUNT_WIDTH 8 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_COUNT_LBN 24 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_COUNT_WIDTH 8 /* MC_CMD_AOE_OUT_MC_SPI_MASTER_READ msgresponse */ #define MC_CMD_AOE_OUT_MC_SPI_MASTER_READ_LEN 4 #define MC_CMD_AOE_OUT_MC_SPI_MASTER_READ_DATA_OFST 0 /* MC_CMD_AOE_OUT_MC_SPI_MASTER_WRITE msgresponse */ #define MC_CMD_AOE_OUT_MC_SPI_MASTER_WRITE_LEN 0 /* MC_CMD_AOE_OUT_MC_SPI_MASTER msgresponse */ #define MC_CMD_AOE_OUT_MC_SPI_MASTER_LEN 0 /***********************************/ /* MC_CMD_PTP * Perform PTP operation */ #define MC_CMD_PTP 0xb /* MC_CMD_PTP_IN msgrequest */ #define MC_CMD_PTP_IN_LEN 1 #define MC_CMD_PTP_IN_OP_OFST 0 #define MC_CMD_PTP_IN_OP_LEN 1 #define MC_CMD_PTP_OP_ENABLE 0x1 /* enum */ #define MC_CMD_PTP_OP_DISABLE 0x2 /* enum */ #define MC_CMD_PTP_OP_TRANSMIT 0x3 /* enum */ #define MC_CMD_PTP_OP_READ_NIC_TIME 0x4 /* enum */ #define MC_CMD_PTP_OP_STATUS 0x5 /* enum */ #define MC_CMD_PTP_OP_ADJUST 0x6 /* enum */ #define MC_CMD_PTP_OP_SYNCHRONIZE 0x7 /* enum */ #define MC_CMD_PTP_OP_MANFTEST_BASIC 0x8 /* enum */ #define MC_CMD_PTP_OP_MANFTEST_PACKET 0x9 /* enum */ #define MC_CMD_PTP_OP_RESET_STATS 0xa /* enum */ #define MC_CMD_PTP_OP_DEBUG 0xb /* enum */ #define MC_CMD_PTP_OP_FPGAREAD 0xc /* enum */ #define MC_CMD_PTP_OP_FPGAWRITE 0xd /* enum */ #define MC_CMD_PTP_OP_CLOCK_OFFSET_ADJUST 0xe /* enum */ #define MC_CMD_PTP_OP_CLOCK_FREQ_ADJUST 0xf /* enum */ #define MC_CMD_PTP_OP_RX_SET_VLAN_FILTER 0x10 /* enum */ #define MC_CMD_PTP_OP_RX_SET_UUID_FILTER 0x11 /* enum */ #define MC_CMD_PTP_OP_RX_SET_DOMAIN_FILTER 0x12 /* enum */ #define MC_CMD_PTP_OP_SET_CLK_SRC 0x13 /* enum */ #define MC_CMD_PTP_OP_RST_CLK 0x14 /* enum */ #define MC_CMD_PTP_OP_PPS_ENABLE 0x15 /* enum */ #define MC_CMD_PTP_OP_MAX 0x16 /* enum */ /* MC_CMD_PTP_IN_ENABLE msgrequest */ #define MC_CMD_PTP_IN_ENABLE_LEN 16 #define MC_CMD_PTP_IN_CMD_OFST 0 #define MC_CMD_PTP_IN_PERIPH_ID_OFST 4 #define MC_CMD_PTP_IN_ENABLE_QUEUE_OFST 8 #define MC_CMD_PTP_IN_ENABLE_MODE_OFST 12 #define MC_CMD_PTP_MODE_V1 0x0 /* enum */ #define MC_CMD_PTP_MODE_V1_VLAN 0x1 /* enum */ #define MC_CMD_PTP_MODE_V2 0x2 /* enum */ #define MC_CMD_PTP_MODE_V2_VLAN 0x3 /* enum */ #define MC_CMD_PTP_MODE_V2_ENHANCED 0x4 /* enum */ /* MC_CMD_PTP_IN_DISABLE msgrequest */ #define MC_CMD_PTP_IN_DISABLE_LEN 8 /* MC_CMD_PTP_IN_CMD_OFST 0 */ /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ /* MC_CMD_PTP_IN_TRANSMIT msgrequest */ #define MC_CMD_PTP_IN_TRANSMIT_LENMIN 13 #define MC_CMD_PTP_IN_TRANSMIT_LENMAX 252 #define MC_CMD_PTP_IN_TRANSMIT_LEN(num) (12+1*(num)) /* MC_CMD_PTP_IN_CMD_OFST 0 */ /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ #define MC_CMD_PTP_IN_TRANSMIT_LENGTH_OFST 8 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_OFST 12 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_LEN 1 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_MINNUM 1 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_MAXNUM 240 /* MC_CMD_PTP_IN_READ_NIC_TIME msgrequest */ #define MC_CMD_PTP_IN_READ_NIC_TIME_LEN 8 /* MC_CMD_PTP_IN_CMD_OFST 0 */ /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ /* MC_CMD_PTP_IN_STATUS msgrequest */ #define MC_CMD_PTP_IN_STATUS_LEN 8 /* MC_CMD_PTP_IN_CMD_OFST 0 */ /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ /* MC_CMD_PTP_IN_ADJUST msgrequest */ #define MC_CMD_PTP_IN_ADJUST_LEN 24 /* MC_CMD_PTP_IN_CMD_OFST 0 */ /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ #define MC_CMD_PTP_IN_ADJUST_FREQ_OFST 8 #define MC_CMD_PTP_IN_ADJUST_FREQ_LEN 8 #define MC_CMD_PTP_IN_ADJUST_FREQ_LO_OFST 8 #define MC_CMD_PTP_IN_ADJUST_FREQ_HI_OFST 12 #define MC_CMD_PTP_IN_ADJUST_BITS 0x28 /* enum */ #define MC_CMD_PTP_IN_ADJUST_SECONDS_OFST 16 #define MC_CMD_PTP_IN_ADJUST_NANOSECONDS_OFST 20 /* MC_CMD_PTP_IN_SYNCHRONIZE msgrequest */ #define MC_CMD_PTP_IN_SYNCHRONIZE_LEN 20 /* MC_CMD_PTP_IN_CMD_OFST 0 */ /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ #define MC_CMD_PTP_IN_SYNCHRONIZE_NUMTIMESETS_OFST 8 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_OFST 12 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LEN 8 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LO_OFST 12 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_HI_OFST 16 /* MC_CMD_PTP_IN_MANFTEST_BASIC msgrequest */ #define MC_CMD_PTP_IN_MANFTEST_BASIC_LEN 8 /* MC_CMD_PTP_IN_CMD_OFST 0 */ /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ /* MC_CMD_PTP_IN_MANFTEST_PACKET msgrequest */ #define MC_CMD_PTP_IN_MANFTEST_PACKET_LEN 12 /* MC_CMD_PTP_IN_CMD_OFST 0 */ /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ #define MC_CMD_PTP_IN_MANFTEST_PACKET_TEST_ENABLE_OFST 8 /* MC_CMD_PTP_IN_RESET_STATS msgrequest */ #define MC_CMD_PTP_IN_RESET_STATS_LEN 8 /* MC_CMD_PTP_IN_CMD_OFST 0 */ /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ /* MC_CMD_PTP_IN_DEBUG msgrequest */ #define MC_CMD_PTP_IN_DEBUG_LEN 12 /* MC_CMD_PTP_IN_CMD_OFST 0 */ /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ #define MC_CMD_PTP_IN_DEBUG_DEBUG_PARAM_OFST 8 /* MC_CMD_PTP_IN_FPGAREAD msgrequest */ #define MC_CMD_PTP_IN_FPGAREAD_LEN 16 /* MC_CMD_PTP_IN_CMD_OFST 0 */ /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ #define MC_CMD_PTP_IN_FPGAREAD_ADDR_OFST 8 #define MC_CMD_PTP_IN_FPGAREAD_NUMBYTES_OFST 12 /* MC_CMD_PTP_IN_FPGAWRITE msgrequest */ #define MC_CMD_PTP_IN_FPGAWRITE_LENMIN 13 #define MC_CMD_PTP_IN_FPGAWRITE_LENMAX 252 #define MC_CMD_PTP_IN_FPGAWRITE_LEN(num) (12+1*(num)) /* MC_CMD_PTP_IN_CMD_OFST 0 */ /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ #define MC_CMD_PTP_IN_FPGAWRITE_ADDR_OFST 8 #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_OFST 12 #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_LEN 1 #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_MINNUM 1 #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_MAXNUM 240 /* MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST msgrequest */ #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_LEN 16 /* MC_CMD_PTP_IN_CMD_OFST 0 */ /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_SECONDS_OFST 8 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_NANOSECONDS_OFST 12 /* MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST msgrequest */ #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_LEN 16 /* MC_CMD_PTP_IN_CMD_OFST 0 */ /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_OFST 8 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LEN 8 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LO_OFST 8 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_HI_OFST 12 /* MC_CMD_PTP_IN_ADJUST_BITS 0x28 */ /* MC_CMD_PTP_IN_RX_SET_VLAN_FILTER msgrequest */ #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_LEN 24 /* MC_CMD_PTP_IN_CMD_OFST 0 */ /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_NUM_VLAN_TAGS_OFST 8 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_OFST 12 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_LEN 4 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_NUM 3 /* MC_CMD_PTP_IN_RX_SET_UUID_FILTER msgrequest */ #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_LEN 20 /* MC_CMD_PTP_IN_CMD_OFST 0 */ /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_ENABLE_OFST 8 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_OFST 12 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LEN 8 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LO_OFST 12 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_HI_OFST 16 /* MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER msgrequest */ #define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_LEN 16 /* MC_CMD_PTP_IN_CMD_OFST 0 */ /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ #define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_ENABLE_OFST 8 #define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_DOMAIN_OFST 12 /* MC_CMD_PTP_IN_PPS_ENABLE msgrequest */ #define MC_CMD_PTP_IN_PPS_ENABLE_LEN 12 /* MC_CMD_PTP_IN_CMD_OFST 0 */ #define MC_CMD_PTP_IN_PPS_ENABLE_OP_OFST 4 #define MC_CMD_PTP_ENABLE_PPS 0x0 /* enum */ #define MC_CMD_PTP_DISABLE_PPS 0x1 /* enum */ #define MC_CMD_PTP_IN_PPS_ENABLE_QUEUE_ID_OFST 8 /* MC_CMD_PTP_OUT msgresponse */ #define MC_CMD_PTP_OUT_LEN 0 /* MC_CMD_PTP_OUT_TRANSMIT msgresponse */ #define MC_CMD_PTP_OUT_TRANSMIT_LEN 8 #define MC_CMD_PTP_OUT_TRANSMIT_SECONDS_OFST 0 #define MC_CMD_PTP_OUT_TRANSMIT_NANOSECONDS_OFST 4 /* MC_CMD_PTP_OUT_READ_NIC_TIME msgresponse */ #define MC_CMD_PTP_OUT_READ_NIC_TIME_LEN 8 #define MC_CMD_PTP_OUT_READ_NIC_TIME_SECONDS_OFST 0 #define MC_CMD_PTP_OUT_READ_NIC_TIME_NANOSECONDS_OFST 4 /* MC_CMD_PTP_OUT_STATUS msgresponse */ #define MC_CMD_PTP_OUT_STATUS_LEN 64 #define MC_CMD_PTP_OUT_STATUS_CLOCK_FREQ_OFST 0 #define MC_CMD_PTP_OUT_STATUS_STATS_TX_OFST 4 #define MC_CMD_PTP_OUT_STATUS_STATS_RX_OFST 8 #define MC_CMD_PTP_OUT_STATUS_STATS_TS_OFST 12 #define MC_CMD_PTP_OUT_STATUS_STATS_FM_OFST 16 #define MC_CMD_PTP_OUT_STATUS_STATS_NFM_OFST 20 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFLOW_OFST 24 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_BAD_OFST 28 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MIN_OFST 32 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MAX_OFST 36 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_LAST_OFST 40 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MEAN_OFST 44 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MIN_OFST 48 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MAX_OFST 52 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_LAST_OFST 56 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MEAN_OFST 60 /* MC_CMD_PTP_OUT_SYNCHRONIZE msgresponse */ #define MC_CMD_PTP_OUT_SYNCHRONIZE_LENMIN 20 #define MC_CMD_PTP_OUT_SYNCHRONIZE_LENMAX 240 #define MC_CMD_PTP_OUT_SYNCHRONIZE_LEN(num) (0+20*(num)) #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_OFST 0 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_LEN 20 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MINNUM 1 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MAXNUM 12 #define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTSTART_OFST 0 #define MC_CMD_PTP_OUT_SYNCHRONIZE_SECONDS_OFST 4 #define MC_CMD_PTP_OUT_SYNCHRONIZE_NANOSECONDS_OFST 8 #define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTEND_OFST 12 #define MC_CMD_PTP_OUT_SYNCHRONIZE_WAITNS_OFST 16 /* MC_CMD_PTP_OUT_MANFTEST_BASIC msgresponse */ #define MC_CMD_PTP_OUT_MANFTEST_BASIC_LEN 8 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_RESULT_OFST 0 #define MC_CMD_PTP_MANF_SUCCESS 0x0 /* enum */ #define MC_CMD_PTP_MANF_FPGA_LOAD 0x1 /* enum */ #define MC_CMD_PTP_MANF_FPGA_VERSION 0x2 /* enum */ #define MC_CMD_PTP_MANF_FPGA_REGISTERS 0x3 /* enum */ #define MC_CMD_PTP_MANF_OSCILLATOR 0x4 /* enum */ #define MC_CMD_PTP_MANF_TIMESTAMPS 0x5 /* enum */ #define MC_CMD_PTP_MANF_PACKET_COUNT 0x6 /* enum */ #define MC_CMD_PTP_MANF_FILTER_COUNT 0x7 /* enum */ #define MC_CMD_PTP_MANF_PACKET_ENOUGH 0x8 /* enum */ #define MC_CMD_PTP_MANF_GPIO_TRIGGER 0x9 /* enum */ #define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_EXTOSC_OFST 4 /* MC_CMD_PTP_OUT_MANFTEST_PACKET msgresponse */ #define MC_CMD_PTP_OUT_MANFTEST_PACKET_LEN 12 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_RESULT_OFST 0 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FPGACOUNT_OFST 4 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FILTERCOUNT_OFST 8 /* MC_CMD_PTP_OUT_FPGAREAD msgresponse */ #define MC_CMD_PTP_OUT_FPGAREAD_LENMIN 1 #define MC_CMD_PTP_OUT_FPGAREAD_LENMAX 252 #define MC_CMD_PTP_OUT_FPGAREAD_LEN(num) (0+1*(num)) #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_OFST 0 #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_LEN 1 #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_MINNUM 1 #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_MAXNUM 252 /***********************************/ a540 25 /* MC_CMD_HP * HP specific commands. */ #define MC_CMD_HP 0x54 /* MC_CMD_HP_IN msgrequest */ #define MC_CMD_HP_IN_LEN 16 #define MC_CMD_HP_IN_SUBCMD_OFST 0 #define MC_CMD_HP_IN_OCSD_SUBCMD 0x0 /* enum */ #define MC_CMD_HP_IN_LAST_SUBCMD 0x0 /* enum */ #define MC_CMD_HP_IN_OCSD_ADDR_OFST 4 #define MC_CMD_HP_IN_OCSD_ADDR_LEN 8 #define MC_CMD_HP_IN_OCSD_ADDR_LO_OFST 4 #define MC_CMD_HP_IN_OCSD_ADDR_HI_OFST 8 #define MC_CMD_HP_IN_OCSD_INTERVAL_OFST 12 /* MC_CMD_HP_OUT msgresponse */ #define MC_CMD_HP_OUT_LEN 4 #define MC_CMD_HP_OUT_OCSD_STATUS_OFST 0 #define MC_CMD_HP_OUT_OCSD_STOPPED 0x1 /* enum */ #define MC_CMD_HP_OUT_OCSD_STARTED 0x2 /* enum */ #define MC_CMD_HP_OUT_OCSD_ALREADY_STARTED 0x3 /* enum */ /***********************************/ a720 12 #define MC_CMD_CAPABILITIES_TURBO_LBN 0x1 /* enum */ #define MC_CMD_CAPABILITIES_TURBO_WIDTH 0x1 /* enum */ #define MC_CMD_CAPABILITIES_TURBO_ACTIVE_LBN 0x2 /* enum */ #define MC_CMD_CAPABILITIES_TURBO_ACTIVE_WIDTH 0x1 /* enum */ #define MC_CMD_CAPABILITIES_PTP_LBN 0x3 /* enum */ #define MC_CMD_CAPABILITIES_PTP_WIDTH 0x1 /* enum */ #define MC_CMD_CAPABILITIES_AOE_LBN 0x4 /* enum */ #define MC_CMD_CAPABILITIES_AOE_WIDTH 0x1 /* enum */ #define MC_CMD_CAPABILITIES_AOE_ACTIVE_LBN 0x5 /* enum */ #define MC_CMD_CAPABILITIES_AOE_ACTIVE_WIDTH 0x1 /* enum */ #define MC_CMD_CAPABILITIES_FC_ACTIVE_LBN 0x6 /* enum */ #define MC_CMD_CAPABILITIES_FC_ACTIVE_WIDTH 0x1 /* enum */ d767 1 a767 1 * Set the 16byte seed for the MC pseudo-random generator. d816 23 d940 1 a940 1 #define MC_CMD_PUTS_IN_LENMAX 252 d952 1 a952 1 #define MC_CMD_PUTS_IN_STRING_MAXNUM 240 a1005 2 #define MC_CMD_PHY_CAP_DDM_LBN 12 #define MC_CMD_PHY_CAP_DDM_WIDTH 1 a1173 1 #define MC_CMD_LOOPBACK_AOE_INT_NEAR 0x23 /* enum */ a1219 4 #define MC_CMD_GET_LINK_OUT_LINK_FAULT_RX_LBN 6 #define MC_CMD_GET_LINK_OUT_LINK_FAULT_RX_WIDTH 1 #define MC_CMD_GET_LINK_OUT_LINK_FAULT_TX_LBN 7 #define MC_CMD_GET_LINK_OUT_LINK_FAULT_TX_WIDTH 1 a1680 8 #define MC_CMD_NVRAM_TYPE_FPGA 0xd /* enum */ #define MC_CMD_NVRAM_TYPE_FPGA_BACKUP 0xe /* enum */ #define MC_CMD_NVRAM_TYPE_FC_FW 0xf /* enum */ #define MC_CMD_NVRAM_TYPE_FC_FW_BACKUP 0x10 /* enum */ #define MC_CMD_NVRAM_TYPE_CPLD 0x11 /* enum */ #define MC_CMD_NVRAM_TYPE_LICENSE 0x12 /* enum */ #define MC_CMD_NVRAM_TYPE_FC_LOG 0x13 /* enum */ #define MC_CMD_NVRAM_TYPE_FC_EXTRA 0x14 /* enum */ d1741 1 a1741 1 #define MC_CMD_NVRAM_READ_OUT_LENMAX 252 d1746 1 a1746 1 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MAXNUM 252 d1757 1 a1757 1 #define MC_CMD_NVRAM_WRITE_IN_LENMAX 252 d1767 1 a1767 1 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MAXNUM 240 a1884 15 #define MC_CMD_SENSOR_IN_1V2A 0xd /* enum */ #define MC_CMD_SENSOR_IN_VREF 0xe /* enum */ #define MC_CMD_SENSOR_OUT_VAOE 0xf /* enum */ #define MC_CMD_SENSOR_AOE_TEMP 0x10 /* enum */ #define MC_CMD_SENSOR_PSU_AOE_TEMP 0x11 /* enum */ #define MC_CMD_SENSOR_PSU_TEMP 0x12 /* enum */ #define MC_CMD_SENSOR_FAN_0 0x13 /* enum */ #define MC_CMD_SENSOR_FAN_1 0x14 /* enum */ #define MC_CMD_SENSOR_FAN_2 0x15 /* enum */ #define MC_CMD_SENSOR_FAN_3 0x16 /* enum */ #define MC_CMD_SENSOR_FAN_4 0x17 /* enum */ #define MC_CMD_SENSOR_IN_VAOE 0x18 /* enum */ #define MC_CMD_SENSOR_OUT_IAOE 0x19 /* enum */ #define MC_CMD_SENSOR_IN_IAOE 0x1a /* enum */ #define MC_CMD_SENSOR_NIC_POWER 0x1b /* enum */ d2097 1 a2097 1 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMAX 252 d2103 1 a2103 1 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MAXNUM 248 a2185 68 /***********************************/ /* MC_CMD_CLP * CLP support operations */ #define MC_CMD_CLP 0x56 /* MC_CMD_CLP_IN msgrequest */ #define MC_CMD_CLP_IN_LEN 4 #define MC_CMD_CLP_IN_OP_OFST 0 #define MC_CMD_CLP_OP_DEFAULT 0x1 /* enum */ #define MC_CMD_CLP_OP_SET_MAC 0x2 /* enum */ #define MC_CMD_CLP_OP_GET_MAC 0x3 /* enum */ #define MC_CMD_CLP_OP_SET_BOOT 0x4 /* enum */ #define MC_CMD_CLP_OP_GET_BOOT 0x5 /* enum */ /* MC_CMD_CLP_OUT msgresponse */ #define MC_CMD_CLP_OUT_LEN 0 /* MC_CMD_CLP_IN_DEFAULT msgrequest */ #define MC_CMD_CLP_IN_DEFAULT_LEN 4 /* MC_CMD_CLP_IN_OP_OFST 0 */ /* MC_CMD_CLP_OUT_DEFAULT msgresponse */ #define MC_CMD_CLP_OUT_DEFAULT_LEN 0 /* MC_CMD_CLP_IN_SET_MAC msgrequest */ #define MC_CMD_CLP_IN_SET_MAC_LEN 12 /* MC_CMD_CLP_IN_OP_OFST 0 */ #define MC_CMD_CLP_IN_SET_MAC_ADDR_OFST 4 #define MC_CMD_CLP_IN_SET_MAC_ADDR_LEN 6 #define MC_CMD_CLP_IN_SET_MAC_RESERVED_OFST 10 #define MC_CMD_CLP_IN_SET_MAC_RESERVED_LEN 2 /* MC_CMD_CLP_OUT_SET_MAC msgresponse */ #define MC_CMD_CLP_OUT_SET_MAC_LEN 0 /* MC_CMD_CLP_IN_GET_MAC msgrequest */ #define MC_CMD_CLP_IN_GET_MAC_LEN 4 /* MC_CMD_CLP_IN_OP_OFST 0 */ /* MC_CMD_CLP_OUT_GET_MAC msgresponse */ #define MC_CMD_CLP_OUT_GET_MAC_LEN 8 #define MC_CMD_CLP_OUT_GET_MAC_ADDR_OFST 0 #define MC_CMD_CLP_OUT_GET_MAC_ADDR_LEN 6 #define MC_CMD_CLP_OUT_GET_MAC_RESERVED_OFST 6 #define MC_CMD_CLP_OUT_GET_MAC_RESERVED_LEN 2 /* MC_CMD_CLP_IN_SET_BOOT msgrequest */ #define MC_CMD_CLP_IN_SET_BOOT_LEN 5 /* MC_CMD_CLP_IN_OP_OFST 0 */ #define MC_CMD_CLP_IN_SET_BOOT_FLAG_OFST 4 #define MC_CMD_CLP_IN_SET_BOOT_FLAG_LEN 1 /* MC_CMD_CLP_OUT_SET_BOOT msgresponse */ #define MC_CMD_CLP_OUT_SET_BOOT_LEN 0 /* MC_CMD_CLP_IN_GET_BOOT msgrequest */ #define MC_CMD_CLP_IN_GET_BOOT_LEN 4 /* MC_CMD_CLP_IN_OP_OFST 0 */ /* MC_CMD_CLP_OUT_GET_BOOT msgresponse */ #define MC_CMD_CLP_OUT_GET_BOOT_LEN 4 #define MC_CMD_CLP_OUT_GET_BOOT_FLAG_OFST 0 #define MC_CMD_CLP_OUT_GET_BOOT_FLAG_LEN 1 #define MC_CMD_CLP_OUT_GET_BOOT_RESERVED_OFST 1 #define MC_CMD_CLP_OUT_GET_BOOT_RESERVED_LEN 3 a2294 2 #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_UDP_ONLY_LBN 3 #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_UDP_ONLY_WIDTH 1 a2770 14 /* MC_CMD_TCM_BUCKET_INIT */ #define MC_CMD_TCM_BUCKET_INIT 0x82 /* MC_CMD_TCM_BUCKET_INIT_IN msgrequest */ #define MC_CMD_TCM_BUCKET_INIT_IN_LEN 8 #define MC_CMD_TCM_BUCKET_INIT_IN_BUCKET_OFST 0 #define MC_CMD_TCM_BUCKET_INIT_IN_RATE_OFST 4 /* MC_CMD_TCM_BUCKET_INIT_OUT msgresponse */ #define MC_CMD_TCM_BUCKET_INIT_OUT_LEN 0 /***********************************/ d2773 1 a2773 1 #define MC_CMD_TCM_TXQ_INIT 0x83 CTMFN sys/dev/sfxge/common/siena_nic.c 1004 1004 644 d5635564a213c5d5d16560e0ab774142 aa8198300df0a8e322d5cf0956111419 949 d27 1 a27 1 __FBSDID("$FreeBSD: head/sys/dev/sfxge/common/siena_nic.c 279048 2015-02-20 07:57:59Z arybchik $"); d282 1 a282 2 uint8_t *mac_addr; efx_dword_t *capabilities; d305 2 a306 2 if (emip->emi_port == 1) { mac_addr = MCDI_OUT2(req, uint8_t, d308 2 a309 4 capabilities = MCDI_OUT2(req, efx_dword_t, GET_BOARD_CFG_OUT_CAPABILITIES_PORT0); } else { mac_addr = MCDI_OUT2(req, uint8_t, d311 1 a311 4 capabilities = MCDI_OUT2(req, efx_dword_t, GET_BOARD_CFG_OUT_CAPABILITIES_PORT1); } EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr); a315 13 /* Additional capabilities */ encp->enc_clk_mult = 1; if (MCDI_CMD_DWORD_FIELD(capabilities, CAPABILITIES_TURBO)) { enp->en_features |= EFX_FEATURE_TURBO; if (MCDI_CMD_DWORD_FIELD(capabilities, CAPABILITIES_TURBO_ACTIVE)) encp->enc_clk_mult = 2; } encp->enc_evq_moderation_max = EFX_EV_TIMER_QUANTUM << FRF_AB_TIMER_VAL_WIDTH / encp->enc_clk_mult; d611 3 CTMFN sys/dev/sfxge/sfxge_rx.c 1004 1004 644 0b0614e073be0f13df587a65a78f2982 056a95bef7b9ac872b4e8ba239e2175d 171 d31 1 a31 1 __FBSDID("$FreeBSD: head/sys/dev/sfxge/sfxge_rx.c 279077 2015-02-20 19:39:40Z arybchik $"); d1175 3 a1177 1 for (id = 0; id < nitems(sfxge_rx_stats); id++) { CTMFN sys/dev/sfxge/sfxge_tx.c 1004 1004 644 31a87c6df8209f462590097e245db138 f576772e24fd1c0b6e09167878016fa4 916 d46 1 a46 1 __FBSDID("$FreeBSD: head/sys/dev/sfxge/sfxge_tx.c 279080 2015-02-20 19:44:02Z arybchik $"); a867 2 const struct tcphdr *th; struct tcphdr th_copy; d895 1 a895 12 KASSERT(mbuf->m_len >= tso->tcph_off, ("network header is fragmented in mbuf")); /* We need TCP header including flags (window is the next) */ if (mbuf->m_len < tso->tcph_off + offsetof(struct tcphdr, th_win)) { m_copydata(tso->mbuf, tso->tcph_off, sizeof(th_copy), (caddr_t)&th_copy); th = &th_copy; } else { th = tso_tcph(tso); } tso->header_len = tso->tcph_off + 4 * th->th_off; d898 1 a898 1 tso->seqnum = ntohl(th->th_seq); d901 1 a901 1 KASSERT(!(th->th_flags & (TH_URG | TH_SYN | TH_RST)), d1133 1 a1133 3 if (level <= SFXGE_TXQ_UNBLOCK_LEVEL(txq->entries)) { /* reaped must be in sync with blocked */ sfxge_tx_qreap(txq); a1134 1 } d1538 3 a1540 1 for (id = 0; id < nitems(sfxge_tx_stats); id++) { CTMFN sys/dev/sfxge/sfxge_tx.h 1004 1004 644 16998aec43f55ce76e2f4c33a01a6774 fa81fccd624e84f112d2299de1b11e14 152 d29 1 a29 1 * $FreeBSD: head/sys/dev/sfxge/sfxge_tx.h 279077 2015-02-20 19:39:40Z arybchik $ d44 7 a50 1 #define SFXGE_TX_MAPPING_MAX_SEG (64 / 2 + 1) CTMFN sys/net/if_vlan.c 1004 1004 644 af1231c761929fe72840367c4fdce7b4 dd3b53536c43c2ef9f878c41b5836130 538 d42 1 a42 1 __FBSDID("$FreeBSD: head/sys/net/if_vlan.c 279071 2015-02-20 18:39:12Z delphij $"); a1777 21 case SIOCSIFCAP: VLAN_LOCK(); if (TRUNK(ifv) != NULL) { p = PARENT(ifv); VLAN_UNLOCK(); if ((p->if_type != IFT_ETHER) && (ifr->ifr_reqcap & IFCAP_VLAN_HWTAGGING) == 0) { error = EINVAL; break; } error = (*p->if_ioctl)(p, cmd, data); if (error) break; /* Propogate vlan interface capabilities */ vlan_trunk_capabilities(p); } else { VLAN_UNLOCK(); error = EINVAL; } break; CTMFN sys/powerpc/powermac/powermac_thermal.c 1004 1004 644 3f0297118645048924981ffaf4f27e10 aae0b670cf4cd71642ae11ffc171d75a 850 d28 1 a28 1 __FBSDID("$FreeBSD: head/sys/powerpc/powermac/powermac_thermal.c 279045 2015-02-20 06:19:23Z jhibbits $"); a44 3 /* A 10 second timer for spinning down fans. */ #define FAN_HYSTERESIS_TIMER 10 a65 1 int timer; a97 1 int fan_speed; d140 1 a140 3 temp = imin(sensor->last_val, sensor->sensor->max_temp); frac_excess = (temp - d142 2 a143 1 (sensor->sensor->max_temp - temp + 1); d169 1 a169 2 max_excess_zone = imin(max_excess_zone, 100); fan_speed = max_excess_zone * d171 1 a171 12 fan->fan->min_rpm; if (fan_speed >= fan->last_val) { fan->timer = FAN_HYSTERESIS_TIMER; fan->last_val = fan_speed; } else { fan->timer--; if (fan->timer == 0) { fan->last_val = fan_speed; fan->timer = FAN_HYSTERESIS_TIMER; } } fan->fan->set(fan->fan, fan->last_val); CTMFN sys/x86/acpica/acpi_wakeup.c 1004 1004 644 1a7b740ec57539b9b8d6f8542398036b 4a08858a14af207dd37f35daf9ccaf1c 257 d31 1 a31 1 __FBSDID("$FreeBSD: head/sys/x86/acpica/acpi_wakeup.c 279079 2015-02-20 19:42:26Z tijl $"); a32 5 #if defined(__amd64__) #define DEV_APIC #else #include "opt_apic.h" #endif a57 1 #ifdef DEV_APIC a59 1 #endif a273 1 #ifdef DEV_APIC a274 1 #endif CTMFN usr.sbin/jls/jls.8 1004 1004 644 d2cee09b520900f461b6acdd5110b5d7 c1cb13cdf849dfefa2e5f189e81b7459 202 d26 1 a26 1 .\" $FreeBSD: head/usr.sbin/jls/jls.8 279081 2015-02-20 19:48:24Z jamie $ d95 1 a95 2 Extend the standard display with a multiple-line summary per jail, containing the following parameters: CTMFN usr.sbin/jls/jls.c 1004 1004 644 3477c2988651d55f96d7922bbdc37bf9 3287ac318618268799fbd815cadc47e7 157 d30 1 a30 1 __FBSDID("$FreeBSD: head/usr.sbin/jls/jls.c 279081 2015-02-20 19:48:24Z jamie $"); d169 1 a169 2 } else { pflags &= ~PRINT_VERBOSE; a172 1 } CTM_END 6ac081fe4d8acf64f56d71a5a7cec273